Patents by Inventor William Halpin
William Halpin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10268797Abstract: Methods and apparatuses to design an integrated circuit are discussed. In one embodiment, the method of designing an integrated circuit comprises partitioning a chip resource into a plurality of sections, and calculating the rank of the sections based on a quality metric. The method further comprises removing the sections with the lowest ranks from consideration by a placement transform.Type: GrantFiled: November 21, 2013Date of Patent: April 23, 2019Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin
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Patent number: 9199312Abstract: A cutting insert incorporates a pre-formed discrete cutting tip which wraps around a curved cutting corner of the insert. The cutting tip includes a top layer and a bottom layer made of a relatively harder material than the top layer. In one embodiment, the bottom layer is made of polycrystalline diamond (PCD) or a polycrystalline cubic boron nitride (CBN) material and the top layer is made of cemented carbide. The cutting insert may further incorporate a chip control structure formed in the cutting tip including a plurality of facets formed on each side of a centerline for providing chip control during a cutting operation. The chip control structure can be formed in a two-step process to expose a portion of the bottom layer. The discrete cutting tip can be brazed to the cutting insert prior to forming the chip control structure.Type: GrantFiled: March 7, 2011Date of Patent: December 1, 2015Assignee: KENNAMETAL INC.Inventors: Shi Chen, Kent Peter Mizgalski, Timothy William Halpin, John James Barry, Gerd Willi Heubeck
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Patent number: 8966415Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, a method of designing an integrated circuit comprises determining a state of a design of the integrated circuit at a high level design representation of the integrated circuit, wherein the state of the design of the integrated circuit comprises a netlist with at least one of timing data, resource information, placement information, routing information, and power data. The method further comprises determining a first transform for the state, changing the state of the design at the high level design representation of the integrated circuit using the first transform, and determining a second transform based on the changed state.Type: GrantFiled: October 25, 2013Date of Patent: February 24, 2015Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin
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Patent number: 8880437Abstract: First and second components of the present invention, in combination, provide a customer interface for initiating a trade transaction and provides for the secure viewing of the status of the transaction. A third component assists in the automatic generation and verification of the voluminous and detailed documents required to support a trade transaction. The third component additionally tracks and assists in the management of the seller's manufacturing and shipment of the goods that form the basis of the trade transaction. A fourth component automatically generates a Letter of Credit from a Purchase Order and performs a reconciliation function on payments made pursuant to Letters of Credit or open Accounts.Type: GrantFiled: August 13, 2013Date of Patent: November 4, 2014Assignee: JPMorgan Chase Bank, N.A.Inventors: Albert Kwang-Hwa Sun, Tak Ming Chan, Jaqueline Layer, Nicole Gabrielle Rodriguez Toulis, Stephen Pan Cheung, Patrick Shu Pui Ko, Sammy Shun Yuen Fung, Thomas William Halpin, Yoke Bee Yap, Zeno Fook Chuen Chow, Kelvin Yatsun Leung, Kwok Keung Yeung, Man Pui Tsim, Sol Solomon
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Patent number: 8819608Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate timing information from the placement, and the process is incrementally iterative toward the final timing enclosure of the design. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic.Type: GrantFiled: July 22, 2008Date of Patent: August 26, 2014Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin
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Patent number: 8701068Abstract: An integrated circuit (IC) comprising a shielding mesh in at least one layer of the IC, the shielding mesh having a first plurality of lines which are designed to provide a first reference voltage and having a second plurality of lines which are designed to provide a second reference voltage and wherein the shielding mesh comprises a window in which signal lines are routed with less shielding than signal lines which are routed in the shielding mesh. The IC further comprising power supply lines in at least a first layer of the IC, the first layer being different than the at least one layer which contains the shielding mesh, the power supply lines being coupled to the shielding mesh and being larger in width than the first plurality of lines and the second plurality of lines.Type: GrantFiled: February 22, 2013Date of Patent: April 15, 2014Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, William Halpin
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Publication number: 20140082579Abstract: Methods and apparatuses to design an integrated circuit are discussed. In one embodiment, the method of designing an integrated circuit comprises partitioning a chip resource into a plurality of sections, and calculating the rank of the sections based on a quality metric. The method further comprises removing the sections with the lowest ranks from consideration by a placement transform.Type: ApplicationFiled: November 21, 2013Publication date: March 20, 2014Applicant: Synopsys, Inc.Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin
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Publication number: 20140053120Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, a method of designing an integrated circuit comprises determining a state of a design of the integrated circuit at a high level design representation of the integrated circuit, wherein the state of the design of the integrated circuit comprises a netlist with at least one of timing data, resource information, placement information, routing information, and power data. The method further comprises determining a first transform for the state, changing the state of the design at the high level design representation of the integrated circuit using the first transform, and determining a second transform based on the changed state.Type: ApplicationFiled: October 25, 2013Publication date: February 20, 2014Applicant: Synopsys, Inc.Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin
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Patent number: 8595674Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic. According to another aspect, the present invention circuit design discloses incremental force directed placement transforms utilizing resource layers to address the heterogeneous resource distribution problem, where the force on an instance can be a weighted average of the forces from its resource layers based on the local congestion of those resources.Type: GrantFiled: July 22, 2008Date of Patent: November 26, 2013Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin
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Patent number: 8589850Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate timing information from the placement, and the process is incrementally iterative toward the final timing enclosure of the design. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic.Type: GrantFiled: July 22, 2008Date of Patent: November 19, 2013Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin
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Publication number: 20130246245Abstract: First and second components of the present invention, in combination, provide a customer interface for initiating a trade transaction and provides for the secure viewing of the status of the transaction. A third component assists in the automatic generation and verification of the voluminous and detailed documents required to support a trade transaction. The third component additionally tracks and assists in the management of the seller's manufacturing and shipment of the goods that form the basis of the trade transaction. A fourth component automatically generates a Letter of Credit from a Purchase Order and performs a reconciliation function on payments made pursuant to Letters of Credit or open Accounts.Type: ApplicationFiled: May 1, 2013Publication date: September 19, 2013Applicant: JPMorgan Chase Bank, N.A.Inventors: Albert Kwang-Hwa Sun, Tak Ming Chan, Jacqueline Layer, Nicole Gabrielle Rodriguez Toulis, Stephen Pan Cheung, Patrick Shu Pui KO, Sammy Shun Yuen Fung, Thomas William Halpin, Yoke Bee Yap, Zeno Fook Chuen Chow, Kelvin Yatsun Leung, Kwok Keung Yeung, Man Pui Tsim, Sol Solomon
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Patent number: 8538844Abstract: First and second components of the present invention, in combination, provide a customer interface for initiating a trade transaction and provides for the secure viewing of the status of the transaction. A third component assists in the automatic generation and verification of the voluminous and detailed documents required to support a trade transaction. The third component additionally tracks and assists in the management of the seller's manufacturing and shipment of the goods that form the basis of the trade transaction. A fourth component automatically generates a Letter of Credit from a Purchase Order and performs a reconciliation function on payments made pursuant to Letters of Credit or open Accounts.Type: GrantFiled: February 16, 2011Date of Patent: September 17, 2013Assignee: JPMorgan Chase Bank, N.A.Inventors: Albert Kwang-Hwa Sun, Tak Ming Chan, Jacqueline Layer, Nicole Gabrielle Rodriguez Toulis, Stephen Pan Cheung, Patrick Shu Pui Ko, Sammy Shun Yuen Fung, Thomas William Halpin, Yoke Bee Yap, Zeno Fook Cheun Chow, Kelvin Yatsun Leung, Kwok Keung Yeung, Man Pui Tsim
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Publication number: 20130162346Abstract: An integrated circuit (IC) comprising a shielding mesh in at least one layer of the IC, the shielding mesh having a first plurality of lines which are designed to provide a first reference voltage and having a second plurality of lines which are designed to provide a second reference voltage and wherein the shielding mesh comprises a window in which signal lines are routed with less shielding than signal lines which are routed in the shielding mesh. The IC further comprising power supply lines in at least a first layer of the IC, the first layer being different than the at least one layer which contains the shielding mesh, the power supply lines being coupled to the shielding mesh and being larger in width than the first plurality of lines and the second plurality of lines.Type: ApplicationFiled: February 22, 2013Publication date: June 27, 2013Inventors: Kenneth S. McElvain, William Halpin
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Patent number: 8386979Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.Type: GrantFiled: January 22, 2009Date of Patent: February 26, 2013Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, William Halpin
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Publication number: 20120230785Abstract: A cutting insert incorporates a pre-formed discrete cutting tip which wraps around a curved cutting corner of the insert. The cutting tip includes a top layer and a bottom layer made of a relatively harder material than the top layer. In one embodiment, the bottom layer is made of polycrystalline diamond (PCD) or a polycrystalline cubic boron nitride (CBN) material and the top layer is made of cemented carbide. The cutting insert may further incorporate a chip control structure formed in the cutting tip including a plurality of facets formed on each side of a centerline for providing chip control during a cutting operation. The chip control structure can be formed in a two-step process to expose a portion of the bottom layer. The discrete cutting tip can be brazed to the cutting insert prior to forming the chip control structure.Type: ApplicationFiled: March 7, 2011Publication date: September 13, 2012Applicant: KENNAMETAL INC.Inventors: Shi Chen, Kent Peter Mizgalski, Timothy William Halpin, John James Barry, Gerd Willi Heubeck
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Patent number: 8171441Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.Type: GrantFiled: January 22, 2009Date of Patent: May 1, 2012Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, William Halpin
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Patent number: 8166434Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.Type: GrantFiled: January 22, 2009Date of Patent: April 24, 2012Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, William Halpin
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Patent number: 8161442Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.Type: GrantFiled: January 22, 2009Date of Patent: April 17, 2012Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, William Halpin
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Patent number: 8122412Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.Type: GrantFiled: January 22, 2009Date of Patent: February 21, 2012Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, William Halpin
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Patent number: 8074197Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.Type: GrantFiled: January 22, 2009Date of Patent: December 6, 2011Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, William Halpin