Abstract: A differential error detector includes a first DC coupler having a signal input that receives a first signal component of a differential signal representing a predesignated series of logic states, and a second DC coupler having a signal input that receives a second signal component of the differential signal representing a complement of the series of logic states, wherein at least two types of logic bits are encoded according to at least two corresponding differential amplitudes between the first signal component and the second signal component. A DC source coupled between a bias input of the first DC coupler and a bias input of the second DC coupler imposes an offset between the first signal component and the second signal component. The offset selectively reduces the differential amplitude of one of the types of encoded logic bits between a signal output of the first DC coupler and a signal output of the second DC coupler.