Patents by Inventor William Harry Nagel

William Harry Nagel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hardware enhancements to radial basis function with restricted coulomb energy learning and/or k-Nearest Neighbor based neural network classifiers
    Patent number: 9747547
    Abstract: A nonlinear neuron classifier comprising a neuron array including a plurality of neuron chips each including a plurality of neurons of variable length and variable depth, the chips processing input vectors of variable length and variable depth that are input into the classifier for comparison against vectors stored in the classifier, wherein an NSP flag is set for a plurality of the neurons to indicate that only that plurality of neurons is to participate in the vector calculations. A virtual content addressable memory flag is set for certain of the neuron chips to enable functions including fast readout of data from the chips. Results of vector calculations are aggregated for fast readout for a host computer interfacing with the classifier.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: August 29, 2017
    Assignee: in2H2
    Inventors: Bruce Kent McCormick, William Harry Nagel, Christopher John McCormick, Mickey Lee Fandrich, Vardan Movsisyan, Matthew McCormick
  • HARDWARE ENHANCEMENTS TO RADIAL BASIS FUNCTION WITH RESTRICTED COULOMB ENERGY LEARNING AND/OR K-NEAREST NEIGHBOR BASED NEURAL NETWORK CLASSIFIERS
    Publication number: 20160155048
    Abstract: A nonlinear neuron classifier comprising a neuron array including a plurality of neuron chips each including a plurality of neurons of variable length and variable depth, the chips processing input vectors of variable length and variable depth that are input into the classifier for comparison against vectors stored in the classifier, wherein an NSP flag is set for a plurality of the neurons to indicate that only that plurality of neurons is to participate in the vector calculations. A virtual content addressable memory flag is set for certain of the neuron chips to enable functions including fast readout of data from the chips. Results of vector calculations are aggregated for fast readout for a host computer interfacing with the classifier.
    Type: Application
    Filed: January 21, 2016
    Publication date: June 2, 2016
    Inventors: Bruce Kent McCormick, William Harry Nagel, Christopher John McCormick, Mickey Lee Fandrich, Vardan Movsisyan, Matthew McCormick