Patents by Inventor William Hart

William Hart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7154515
    Abstract: A method and apparatus for eliminating artifacts in images formed using more than one image segment. A buffer region associated with two adjacent image segments is defined wherein the intensity levels of the pixels are attenuated. When image segments substantially overlap in the buffer region, the intensity in the buffer region substantially sums to full scale. The intensity of the pixels in the buffer region is preferably attenuated using a device to modulate the intensity of the source of radiation.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: December 26, 2006
    Assignee: PerkinElmer, Inc.
    Inventors: Joseph P. Donahue, William A. Hart
  • Publication number: 20060269591
    Abstract: The invention is a discrete patch suitable for use in the treatment of a viral lesion, which patch includes a backing layer and an adhesive layer, where the adhesive layer is substantially free of hydrocolloid particles, and the patch has a thickness ranging from about 10 microns to about 1,500 microns and is substantially free of topical anti-acne agents, and methods for treating viral lesions where a discrete patch of the invention is applied to a viral lesion and maintained in contact therewith for a time effective to substantially complete re-epithelialization of the lesion.
    Type: Application
    Filed: May 25, 2006
    Publication date: November 30, 2006
    Inventor: William Hart
  • Publication number: 20060269592
    Abstract: The invention is a discrete patch suitable for use in the treatment of a viral lesion, which patch includes a backing layer and an adhesive layer, where the adhesive layer is substantially free of hydrocolloid particles, and the patch has a thickness ranging from about 10 microns to about 1,500 microns and is substantially free of topical anti-acne agents, and methods for treating viral lesions where a discrete patch of the invention is applied to a viral lesion and maintained in contact therewith for a time effective to substantially complete re-epithelialization of the lesion.
    Type: Application
    Filed: May 24, 2006
    Publication date: November 30, 2006
    Inventor: William Hart
  • Patent number: 6958331
    Abstract: The invention relates to sulfonyl amine derivatives of formula IA wherein R5A, X1, X2, R9 and R10 are as defined herein, which derivatives are useful as bradykinin B1 receptor antagonists.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: October 25, 2005
    Assignee: Novartis AG
    Inventors: Christopher Thomas Brain, William Cantrell, Andrew James Culshaw, Edward Karol Dziadulewicz, Terance William Hart, Timothy John Ritchie, Liladhar Waykole
  • Publication number: 20050031162
    Abstract: A method for monitoring the status of documents created by a large scale document production and management processes. The production and management process may be comprised of a plurality of different stages including: utilizing a print stream to generate the documents, printing documents on a printer in accordance with the print stream, and forming completed mail pieces on an inserter from the printed documents in accordance with mail piece creation data files. A monitoring system receives information regarding the status of individual documents within these production and management process stages. A user may then select one of the stages for closer inspection of the status of documents.
    Type: Application
    Filed: October 25, 2002
    Publication date: February 10, 2005
    Inventors: Surya Sagi, William Hart, Bruce Barrows
  • Publication number: 20040216303
    Abstract: A thick film current sensing resistor is provided having an input terminal for receiving an electrical current, and an output terminal for outputting the electrical current. A film of resistive material extends between the input and output terminals and is electrically coupled to the input and output terminals so that current flows through the film of resistive material. A pair of sensing terminals are provided to sense a voltage potential across the film of resistive material. The sensed voltage provides an indication of the current. An gap is formed in the film of resistive material between the input and output terminals and the sensing terminals. The length of the gap defines a voltage sensing point of the sensing terminals.
    Type: Application
    Filed: May 1, 2003
    Publication date: November 4, 2004
    Inventors: Carl W. Berlin, Dwadasi H. Sarma, Joel F. Downey, James R. Morken, William Hart, Kevin J. McGirr
  • Patent number: 6791419
    Abstract: A constant gain, constant phase RF power block, e.g., for use in a RF amplifier apparatus. In a preferred embodiment, the power block includes a DC to DC power supply circuit co-located with an RF power transistor device on a common heat sink. The power supply circuit has as an input a varying DC voltage and as outputs a constant supply voltage and a constant bias voltage. The power device has as inputs the constant supply voltage and the constant bias voltage, and further configured to receive and amplify an RF signal. The power supply circuit preferably includes a first laser trimmable resistor for setting the constant supply voltage and a second laser trimmable resistor for setting the bias voltage. In this manner, the constant supply and bias voltages may be easily tuned to a desired level during assembly of the power block device. The input and amplified RF signals are each matched to a relatively high impedance, e.g., approximately fifty ohms.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: September 14, 2004
    Assignee: Ericsson, Inc.
    Inventors: Thomas Moller, William Hart, James Mogel, Robert Bartola
  • Publication number: 20040127533
    Abstract: Sulfonamide derivitives of the formula I wherein R1-R6 are as defined in the description, processes for their production, their use as pharmaceuticals, particularly for use in the treatment or prevention of diseases in which bradykinin B1 receptor activation plays a role or is implicated, and pharmaceutical compositions comprising them.
    Type: Application
    Filed: October 22, 2003
    Publication date: July 1, 2004
    Inventors: Terance William Hart, Timothy John Ritchie
  • Patent number: 6644000
    Abstract: A protective device 104 for hoofed and shod animals fabricated of a durable and flexible material is presented. The protective device 104 includes a base 106 and a wall 108, with the wall designed to enclose a hoof 100 of a bare or shod animal such as a horse or cow. The protective device 104 includes a means for size adjustment 216 such as a sizing opening 214 in combination with a plurality of tread grooves 304, which assists in the adjustment of the size and shape of the hoof to fit a variety of hoofs. The protective device 104 preferably includes a shear-relief portion 302 formed such that the front of a hoof has minimal contact with the device 104. Ease of installation, decreased impact, and improved traction are all benefits provided by the protective device 104 disclosed.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: November 11, 2003
    Inventors: James Clark, James B. Hart, William Hart
  • Publication number: 20030167739
    Abstract: A protective device 104 for hoofed and shod animals fabricated of a durable and flexible material is presented. The protective device 104 includes a base 106 and a wall 108, with the wall designed to enclose a hoof 100 of a bare or shod animal such as a horse or cow. The protective device 104 includes a means for size adjustment 216 such as a sizing opening 214 in combination with a plurality of tread grooves 304, which assists in the adjustment of the size and shape of the hoof to fit a variety of hoofs. The protective device 104 preferably includes a shear-relief portion 302 formed such that the front of a hoof has minimal contact with the device 104. Ease of installation, decreased impact, and improved traction are all benefits provided by the protective device 104 disclosed.
    Type: Application
    Filed: March 11, 2002
    Publication date: September 11, 2003
    Inventors: James Clark, James B. Hart, William Hart
  • Publication number: 20030156122
    Abstract: A method and apparatus for eliminating artifacts in images formed using more than one image segment. A buffer region associated with two adjacent image segments is defined wherein the intensity levels of the pixels are attenuated. When image segments substantially overlap in the buffer region, the intensity in the buffer region substantially sums to full scale. The intensity of the pixels in the buffer region is preferably attenuated using a device to modulate the intensity of the source of radiation.
    Type: Application
    Filed: June 15, 2001
    Publication date: August 21, 2003
    Inventors: Joseph P. Donahue, William A. Hart
  • Publication number: 20030048310
    Abstract: An interactive graphical environment includes a scape (e.g., landscape, streetscape, virtualscape) wherein elements of interest on the scape can be activated. The elements are linked (e.g., hyperlinked) to additional information including additional graphical environments, documents, web sites or images providing more information relating to the elements.
    Type: Application
    Filed: October 4, 2002
    Publication date: March 13, 2003
    Inventor: Matthew William Hart
  • Patent number: 6459600
    Abstract: The present invention provides a method for preventing a fault condition in a DC-DC converter (10, 20, 50) having a first secondary winding (Ns1) coupled to a first synchronous rectifier (SQ1) and a second secondary winding (Ns2) coupled to a second synchronous rectifier (SQ2). The first synchronous rectifier (SQ1) is turned on based on a voltage across the first secondary winding (Ns1) and is turned off based on a first driver signal. The second synchronous rectifier (SQ2) is turned on based on a voltage across the second secondary winding (Ns2) and is turned off based on a second driver signal. The present invention also provides a DC-DC converter (10, 20, 50) wherein a first control circuit is coupled to and controls the first synchronous rectifier (SQ1) pursuant to the method described above, and a second control circuit is coupled to and controls the second synchronous rectifier (SQ2) pursuant to the method described above.
    Type: Grant
    Filed: January 27, 2001
    Date of Patent: October 1, 2002
    Assignee: Ericsson, Inc.
    Inventors: Richard W. Farrington, Claes Svardsjo, William Hart
  • Publication number: 20010033506
    Abstract: The present invention provides a method for preventing a fault condition in a DC-DC converter (10, 20, 50) having a first secondary winding (Ns1) coupled to a first synchronous rectifier (SQ1) and a second secondary winding (Ns2) coupled to a second synchronous rectifier (SQ2). The first synchronous rectifier (SQ1) is turned on based on a voltage across the first secondary winding (Ns1) and is turned off based on a first driver signal. The second synchronous rectifier (SQ2) is turned on based on a voltage across the second secondary winding (Ns2) and is turned off based on a second driver signal. The present invention also provides a DC-DC converter (10, 20, 50) wherein a first control circuit is coupled to and controls the first synchronous rectifier (SQ1) pursuant to the method described above, and a second control circuit is coupled to and controls the second synchronous rectifier (SQ2) pursuant to the method described above.
    Type: Application
    Filed: January 27, 2001
    Publication date: October 25, 2001
    Inventors: Richard W. Farrington, Claes Svardsjo, William Hart
  • Patent number: 6307458
    Abstract: An inductor configuration (50) comprising a three-legged inductor core (20) with a first leg (22), second leg (24), and third leg (26) integrally extending from a base (28). The first leg (22) and second leg (24) are predisposed and spaced about a first surface (30) of the base (28) to form a first channel area (32). The second leg (24) also forms, along with the third leg (26), a second channel area (34) separated from the first channel area (32) by the second leg (24). The inductor also comprises an inductor winding (36) arranged about the inductor core (20) to provide relatively equal magnetic flux through the first leg (22), second leg (24), and third leg (26) when current flows through the inductor winding (36). The inductor configuration may be used as an input or output inductor for a synchronous rectifier circuit (100).
    Type: Grant
    Filed: September 22, 1999
    Date of Patent: October 23, 2001
    Assignee: Ericsson Inc.
    Inventors: Jun Zhang, Richard Farrington, William Hart
  • Patent number: 6256214
    Abstract: A self-driven synchronous rectifier circuit having synchronous rectifiers with floating gates for a power converter or signal transformer. The circuit comprises a transformer (49, 70) having a secondary winding with a first and second terminal, a first synchronous rectifier (SQ1) coupled to the first transformer secondary winding first terminal and having a control terminal floating relative to ground and a first drive circuit coupled to the first synchronous rectifier floating control terminal and controlling the first synchronous rectifier. A first control signal is coupled to the first drive circuit, where the first control signal controls the first drive circuit as a function of a polarity reversal of a voltage across the first transformer (49, 70). A second synchronous rectifier (SQ2) is coupled to the first transformer secondary winding second terminal and has a control terminal floating relative to ground.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: July 3, 2001
    Assignee: Ericsson Inc.
    Inventors: Richard W. Farrington, William Hart
  • Patent number: 6188592
    Abstract: A self-driven synchronous rectifier circuit (50) for a DC—DC power converter. The circuit comprises a primary transformer (16), a first synchronous rectifier (SQ1) coupled to the primary transformer (16), a second synchronous rectifier (SQ2) coupled to the primary transformer (16), an external drive circuit (18). The circuit (50) also comprises a plurality of switches (SQ3, SQ4) controllably coupled to second synchronous rectifier (SQ2). The external drive circuit (18) provides turn-off signaling for both synchronous rectifiers (SQ1, SQ2) Turn-on signaling provided for first synchronous rectifier (SQ1) by the primary transformer (16) turn-on signaling for second synchronous rectifier (SQ2) is provided by the external drive circuit (18).
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: February 13, 2001
    Assignee: Ericsson Inc.
    Inventors: Richard W. Farrington, Claes Svardsjo, William Hart
  • Patent number: 6166927
    Abstract: A push-pull converter for converting an input voltage to a selectable output voltage is disclosed. The push-pull converter includes a pair of primary switches and a pair of primary windings of a transformer. The voltage stress across the primary switches is regulated by means of a clamp capacitor. The clamp capacitor clamps the voltage of the primary switches during the reset of the primary windings of the transformer. An alternate embodiment is also disclosed in which the voltage stress across the primary switches is regulated by means of two clamp capacitors. The clamp capacitor clamps the voltage of the primary switches during the reset of the primary windings of the transformer. The clamp capacitors extend the transformer reset period to include the lagging dead time for the corresponding switches, as well as the complementary powering stage. Current in the output section during the dead times is permitted by means of an additional diode, therein.
    Type: Grant
    Filed: July 23, 1999
    Date of Patent: December 26, 2000
    Assignee: Ericsson Inc.
    Inventors: Richard W. Farrington, William Hart
  • Patent number: 6128206
    Abstract: A rectifier circuit having voltage clamping circuitry is disclosed. The rectifier circuit includes a transformer having a primary winding and a secondary winding and transistor switches each being connected to an end of the secondary winding of the transformer. The rectifier circuit further includes a first diode having an anode terminal connected to a first end of the secondary winding and a second diode having an anode terminal connected to a second end of the secondary winding. The cathode terminals of the first and second diodes are coupled to a capacitor. The energy stemming from voltage spikes and/or high frequency ringing appearing at the transistor switches due to parasitic effects is effectively absorbed by the first and second diodes and collected in the capacitor. The collected energy is recycled to control the operation of the transistor switches.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: October 3, 2000
    Assignee: Ericsson, Inc.
    Inventors: Mark N. Sun, William Hart
  • Patent number: D545137
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: June 26, 2007
    Assignee: Rubbermaid Incorporated
    Inventors: Brian D. Furlong, Joseph Lutgen, William Hart