Abstract: Systems and methods are provided for marking integrated circuit defects on wafers to facilitate failure analysis. A wafer containing integrated circuits can be tested using a tester. Test data from the tester can be analyzed using integrated circuit design files to identify suspected faults. A fault location program can be used to identify the physical location of the faults. The fault location program uses information on the faults identified and CAD file information on the physical layout of the integrated circuit to map identified faults to actual physical positions. The fault location program may also generate laser control files. The laser control files can be used to control a laser system so that the laser system creates laser marks on the wafer surrounding each of the faults. The marked faults can be polished and examined under an electron microscope or analyzed using other failure analysis tools.

Abstract: A method is provided for making submicron contact openings by forming an insulating layer over a substrate and a photoresist layer over the insulating layer. The thick photoresist layer is patterned and etched to form a first opening in the photoresist. A thin photoresist layer is then formed over the integrated circuit which is then patterned and etched to form a second opening inside the first opening. A contact opening is then etched through the insulating layer through the second opening in the thin photoresist.