Abstract: The present invention provides a data processing apparatus and method for predicting instructions in a data processing apparatus. The data processing apparatus comprises a processor core for executing instructions from any of a plurality of instruction sets, and a prefetch unit for prefetching instructions from a memory prior to sending those instructions to the processor core for execution. Further, prediction logic is used to predict which instructions should be prefetched by the prefetch unit, the prediction logic being arranged to review a prefetched instruction to predict whether execution of that prefetched instruction will cause a change in instruction flow, and if so to indicate to the prefetch unit an address within the memory from which a next instruction should be retrieved.

Abstract: The present invention provides a data processing apparatus and method for predicting instructions in a data processing apparatus. The data processing apparatus comprises a processor core for executing instructions from any of a plurality of instruction sets, and a prefetch unit for prefetching instructions from a memory prior to sending those instructions to the processor core for execution. Further, prediction logic is used to predict which instructions should be prefetched by the prefetch unit, the prediction logic being arranged to review a prefetched instruction to predict whether execution of that prefetched instruction will cause a change in instruction flow, and if so to indicate to the prefetch unit an address within the memory from which a next instruction should be retrieved.

Abstract: A data processing system has a CPU linked via a unidirectional read bus and a unidirectional write and address bus to a data memory (e.g., cache, RAM, or disk), in the form of a cache memory. Since the read bus and the write and address bus are only driven in one direction, lost time through reversing the direction of signals travel along a bus is avoided. Read-data words and instruction-data words are transferred from the cache memory to a core of the CPU via the read bus. Instruction-address, read-address, write-address, and write-data words are time division multiplexed on the write and address bus to pass from the core to the cache memory. The system supports burst mode transfer thereby reducing the number of addresses that need to be transferred on the write and address bus thereby releasing bandwidth on this bus for use by write-data words.

Abstract: A cache memory in which the address of a required data item is compared with address data stored in a plurality of tag memory sections, a match indicating that the required data item is stored in a corresponding data memory section, is operable in at least a first and a second mode, whereby:(i) in the first mode, only that one of the data memory sections in which the required data word is stored is enabled for operation once the appropriate data memory section has been identified by an address match with the corresponding tag memory section; and(ii) in the second mode, two or more (and preferably all) of the data memory sections are enabled for operation substantially concurrently with the comparison of the required address and the addresses stored in the tag memory sections, an address match being used to select the output of one of the data memory sections.