Abstract: Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.

Abstract: Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.

Abstract: Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.

Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.

Abstract: Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.

Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.

Abstract: Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.

Abstract: Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.

Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.

Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.

Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.

Abstract: Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.

Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.

Abstract: Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.

Abstract: Methods, apparatus, systems, and data structures may operate to combine block management data with a portion of data, to generate error correction data for the combined portion, and to store the data, the block management data, the error correction data for the combined portion, and error correction data for the data in a memory. Additional embodiments may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combine block management data with the particular sector to generate a modified sector. Additional embodiments may operate to generate or store error correction data for the modified sector and combine the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.

Abstract: Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules. In selected examples, memory blocks and associated error correction code are mixed between multiple levels of memory device hierarchy.

Abstract: Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules. In selected examples, memory blocks and associated error correction code are mixed between multiple levels of memory device hierarchy.

Abstract: Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.

Abstract: A memory device is described that provides increased output data to help evaluate data errors from bit line coupling and floating gate coupling during a read operation. Multiple rows, or pages, of data are read to allow an internal or external decoder to evaluate memory cell data.

Abstract: Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.