Patents by Inventor William Henson

William Henson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200000180
    Abstract: One aspect of this disclosure is a method comprising: receiving, from a camera, a video feed depicting a pair of feet and a scaling object; capturing, with the camera, images of the feet and the scaling object based on the video feed; identifying foot features in each captured image; determining camera positions for each captured image by triangulating the foot features; generating a point cloud in a three-dimensional space by positioning each foot feature in the three-dimensional space based on the camera positions; scaling the point cloud based on the scaling object; segmenting the point cloud into at least a right-foot cluster and a left-foot cluster; fitting a first three-dimensional morphable model to the right-foot cluster according to first foot parameters; and fitting a second three-dimensional morphable model to the left-foot cluster according to second foot parameters. Related systems, apparatus, and methods also are described.
    Type: Application
    Filed: February 16, 2018
    Publication date: January 2, 2020
    Inventors: Jamie Roy SHERRAH, Michael HENSON, William Ryan SMITH
  • Publication number: 20190341696
    Abstract: In an embodiment, an electromagnetic device, comprises a substrate a substrate comprising a dielectric layer and a first conductive layer; at least one dielectric structure comprising at least one non-gaseous dielectric material that forms a first dielectric portion that extends outward from the first side of the substrate, the first dielectric portion having an average dielectric constant and an optional second dielectric portion that extends into an optional via. The at least one dielectric structure is bonded to the substrate by at least one of: a mechanical interlock between the second dielectric portion and the substrate due to the at least one interlocking slot comprising a retrograde surface; an intermediate layer located in between the dielectric structure and the substrate having a roughened surface; or an adhesive material located in between the dielectric structure and the substrate.
    Type: Application
    Filed: April 29, 2019
    Publication date: November 7, 2019
    Inventors: Stephen O'Connor, Gianni Taraschi, Christopher Brown, Kristi Pance, Karl E. Sprentall, Bruce Fitts, Dirk Baars, William Blasius, Murali Sethumadhavan, Roshin Rose George, Michael S. White, Michael Lunt, Sam Henson, John Dobrick
  • Publication number: 20190321262
    Abstract: A safety vial system has a vial adapter subsystem irreversibly mountable to the top of a vial containing a hazardous medicament and a vial base subsystem sealingly engaging a lower portion of the vial adapter subsystem and telescopically movable therein from a first position providing a path for gas sterilization around the vial to a second position wherein the path is closed to form a sterilized expandable, neutral pressure bellows chamber around and below the vial. The device has a removable top cap, a pierceable barrier film, a normally closed needleless valve in fluid communication with a dual lumen spike initially disposed above the film and a frangible product integrity ring holding the activation housing in place for sealed telescopic movement on a main body that surrounds the vial.
    Type: Application
    Filed: April 22, 2019
    Publication date: October 24, 2019
    Applicant: Hospira, Inc.
    Inventors: Christopher William CHUDEK, Jesse Carl FULGHUM, III, Amichai TREVES, Benjamin L. RUSH, Jay Colton ZIGNEGO, Robert William HENSON, Edward Paul BROWKA, David Lee FOSHEE, Theodore J. MOSLER
  • Publication number: 20180166402
    Abstract: A semiconductor device includes a metal thin film such as an eFUSE or a precision resistor above and laterally displaced from an interconnect structure. A first dielectric layer is disposed over the interconnect structure and optionally under the metal thin film, and is adapted to prevent etching of the interconnect structure during patterning of the metal thin film. Contacts to the metal thin film and the interconnect are made through a second dielectric layer that is disposed over the metal thin film and over the interconnect.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Viraj SARDESAI, William HENSON, Domingo FERRER LUPPI, Scott ALLEN, Emre ALPTEKIN
  • Publication number: 20170210610
    Abstract: Provided is a ready-to-install apparatus for dispensing carbonated beverages and/or beverages on draught that incorporates a flow sensor and a pinch valve and may be coupled to the end of a beer line (or any other tubing used for beverage dispensing) without having to be integrated within the line (i.e. eliminating the need to make multiple cuts for the valve, the flow sensor, etc.) The beverage dispensing apparatus reduces foaming by reducing the number of components that come into contact with the fluid and/or interfere with flow. For example, the beverage dispensing apparatus may utilize an external flow sensor to reduce the creation of nucleation sites where CO2 bubbles may form. In another example, a pinch valve may be used to prevent excessive foaming in place of conventional valves that must be placed proximal to the keg.
    Type: Application
    Filed: January 23, 2017
    Publication date: July 27, 2017
    Inventors: Zachary William Henson, Ryan Patrick Sauter, Daniel Steven Martinez
  • Patent number: 9283467
    Abstract: Techniques are disclosed for automating how information about sporting events is captured, processed, and stored for delivery to interested users. In an exemplary embodiment, score data for a sporting event is captured at a score source and communicated to a remote destination over a network as a URL request where score data is included in a portion of the URL following a domain name portion. In another exemplary embodiment, a scoreboard identifier and sporting event schedule data is used to determine how to translate received score data prior to loading in a database.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: March 15, 2016
    Assignee: Scorezone, LLC
    Inventors: Scott S. Moore, Gary Wayne Robert, William Henson Purcell, IV, David Lee Paslay
  • Patent number: 8029020
    Abstract: A trailer jack stand for supporting a trailer comprising: a pedestal stand, where stand attaches to a trailer jack, said stand includes a top connecting section and a pivoting section; a center mount pin, where the mount pin attaches the stand to the jack through the top connecting section; a locking pin, where the locking pin secures the mount pin into place; a platform, where the platform attaches to the bottom of the pivoting section; and a spring assembly, where the spring assembly includes a top pivot pin extending from the top connecting section, a stand pin extending from the pivoting section and a spring attached between the pivot pin and stand pin. The pivoting section is capable of pivoting between a retracted position and an extended position, where in the extended position the stand supports the trailer.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: October 4, 2011
    Inventors: William Henson, Debbie Henson
  • Publication number: 20110156379
    Abstract: A trailer jack stand for supporting a trailer comprising: a pedestal stand, where stand attaches to a trailer jack, said stand includes a top connecting section and a pivoting section; a center mount pin, where the mount pin attaches the stand to the jack through the top connecting section; a locking pin, where the locking pin secures the mount pin into place; a platform, where the platform attaches to the bottom of the pivoting section; and a spring assembly, where the spring assembly includes a top pivot pin extending from the top connecting section, a stand pin extending from the pivoting section and a spring attached between the pivot pin and stand pin. The pivoting section is capable of pivoting between a refracted position and an extended position, where in the extended position the stand supports the trailer.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 30, 2011
    Inventors: WILLIAM HENSON, Debbie Henson
  • Patent number: 7574390
    Abstract: In an embodiment of a method of financing an entity, such as an asset management firm, a financing provider invests assets in the entity. The financing provider receives a revenue share interest in the financed entity. No ownership interest in the entity is given to the financing provider during the term of the revenue share interest, and no debt is used. To evaluate and price the investment, a revenue forecasting model may be used.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: August 11, 2009
    Assignee: Asset Management Finance LLC
    Inventors: William Henson, Robert Jakacki, Norton Reamer, Alexander von York
  • Publication number: 20070254423
    Abstract: The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 1, 2007
    Applicant: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Ricardo Donaton, William Henson, Kern Rim
  • Publication number: 20070254478
    Abstract: A method for fabricating a silicide gate field effect transistor includes masking a silicon source/drain region prior to forming the silicide gate by annealing a metal silicide forming metal layer contacting a silicon-containing gate. The silicide gate may be either a fully silicided gate or a partially silicided gate. After unmasking the source/drain region a silicide layer may be formed upon the source/drain region, and also upon the partially silicided gate. The second silicide layer and the partially silicided gate also provide a fully silicided gate.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 1, 2007
    Applicant: International Business Machines Corporation
    Inventors: Zhijiong Luo, William Henson, Christian Lavoie, Huilong Zhu
  • Publication number: 20070254422
    Abstract: A semiconductor structure and method of manufacturing and more particularly a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET. The PFET region and the NFET region having a different sized gate to vary the device performance of the NFET and the PFET.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 1, 2007
    Applicant: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Ricardo Donaton, William Henson, Kern Rim
  • Publication number: 20070235759
    Abstract: An integration scheme for providing Si gates for nFET devices and SiGe gates for pFET devices on the same semiconductor substrate is provided. The integration scheme includes first providing a material stack comprising, from bottom to top, a gate dielectric, a Si film, and a hard mask on a surface of a semiconductor substrate that includes at least one nFET device region and at least one pFET device region. Next, the hard mask is selectively removed from the material stack in the at least one pFET device region thereby exposing the Si film. The exposed Si film is then converted into a SiGe film and thereafter at least one nFET device is formed in the least one nFET device region and at least one pFET device is formed in the at least one pFET device region. In accordance with the present invention, the least one nFET device includes a Si gate and the at least one pFET includes a SiGe gate.
    Type: Application
    Filed: April 11, 2006
    Publication date: October 11, 2007
    Applicant: International Business Machines Corporation
    Inventors: William Henson, Yaocheng Liu, Alexander Reznicek, Kern Rim, Devendra Sadana
  • Publication number: 20070228458
    Abstract: An integration scheme that enables full silicidation (FUSI) of the nFET and pFET gate electrodes at the same time as that of the source/drain regions is provided. The FUSI of the gate electrodes eliminates the gate depletion problem that is observed with polysilicon gate electrodes. In addition, the inventive integration scheme creates different silicon thicknesses of the gate electrode just prior to silicidation. This feature of the present invention allows for fabricating nFETs and pFETs that have a band edge workfunction that is tailored for the specific device region.
    Type: Application
    Filed: March 29, 2006
    Publication date: October 4, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William Henson, Kern Rim, Jack Mandelman
  • Publication number: 20070212861
    Abstract: A sheet resistance stabilized recrystallized antimony doped region may be formed within a semiconductor substrate by annealing a corresponding antimony doped amorphized region at a temperature from about 1050° C. to about 1400° C. for a time period from about 0.1 to about 10 milliseconds. Preferably, a laser surface treatment is used. The laser surface treatment preferably uses a solid phase epitaxy. In addition, the antimony doped region may be co-doped with at least one of a phosphorus dopant and an arsenic dopant. The antimony dopant and the laser surface treatment lend sheet resistance stability that is otherwise absent when forming solely phosphorus and/or arsenic doped regions.
    Type: Application
    Filed: March 7, 2006
    Publication date: September 13, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, Sameer Jain, William Henson, Kern Rim
  • Publication number: 20070131123
    Abstract: A mold form fryer utilizing a top conveyor that transports snack pieces through a constant velocity oil stream without the need for a bottom mating mold or conveyor. Herein, the form fryer is provided with a top conveyor disposed above a fryer oil pan positioned longitudinally through the fryer. Uncooked snack pieces are provided to the fryer oil pan by a bottom entrance conveyor. Snack pieces, once in oil within the fryer, meet with a top conveyor having convex molding surfaces with product-centering elements. At the exit portion of the fryer, a bottom exit conveyor receives the cooked snack pieces from the top conveyor. As no continuous bottom conveyor is utilized, the fryer oil pan may be provided with a reduced volume segment situated between the bottom entrance and exit conveyors.
    Type: Application
    Filed: February 15, 2007
    Publication date: June 14, 2007
    Inventors: William Henson, Harold McKay, Donald Tatsch
  • Publication number: 20070122965
    Abstract: A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.
    Type: Application
    Filed: January 30, 2007
    Publication date: May 31, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, William Henson, Kern Rim, William Wille
  • Publication number: 20070123042
    Abstract: Methods of fabricating a semiconductor structure including heterogeneous suicides or germanides located in different regions of a semiconductor structure are provided. The heterogeneous suicides or germanides are formed onto a semiconductor layer, a conductive layer or both. In accordance with the present invention, the inventive methods utilize a combination of sequential deposition of different metals and patterning to form different suicides or germanides in different regions of a semiconductor chip. The method includes providing a Si-containing or Ge layer having at least a first region and a second region; forming a first silicide or germanide on one of the first or second regions; and forming a second silicide or germanide that is compositionally different from the first silicide or germanide on the other region not including the first silicide or germanide, wherein the steps of forming the first and second suicides or germanides are performed sequentially or in a single step.
    Type: Application
    Filed: November 28, 2005
    Publication date: May 31, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kern Rim, John Ellis-Monaghan, Brian Greene, William Henson, Robert Purtell, Clement Wann, Horatio Wildman
  • Publication number: 20070099362
    Abstract: A method for making a semiconductor device structure includes producing a substrate having formed thereon a gate with spacers, respective source and drain regions adjacent to the gate and an; disposing a first metallic layer on the gate with spacers, and the source and drain regions, disposing a second metallic layer on the first metallic layer; doping the first metallic layer with a first dopant through a portion of the second metal layer disposed over the second gate with spacers; and then heating the intermediate structure to a temperature and for a time sufficient to form a silicide of the first metallic layer. This first layer is, for example, Ni while the second layer is, for example, TiN.
    Type: Application
    Filed: October 31, 2005
    Publication date: May 3, 2007
    Inventors: Dureseti Chidambarrao, William Henson
  • Publication number: 20070069294
    Abstract: A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 29, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, William Henson, Kern Rim, William Wille