Abstract: One embodiment is a system adapted to encrypt one or more packets of plaintext data in cipher-block chaining (CBC) mode. The system includes a plurality of digital logic components connected in series, where respective components are operative to process one or more rounds of a block cipher algorithm. A plurality of N bit registers are respectively coupled to the plurality of digital logic components. An XOR component receives blocks of plaintext data and blocks of ciphertext data, and XORs blocks of plaintext data for respective plaintext packets with previously encrypted blocks of ciphertext data for those plaintext packets. The XOR component iteratively feeds the XOR'd blocks of data into a first of the plurality of the digital logic components. In addition, a circuit component is operative to selectively pass blocks of ciphertext data fed back from an output of a final logic component to the XOR component.

Abstract: The present invention pertains to data security, and more particularly to the security of encrypted data that can be transmitted between computers and the like, as well as stored upon one or more computer systems. A technique is disclosed for efficiently implementing the Rijndael inverse cipher. In this manner, encrypted ciphertext can be efficiently decrypted or converted back into plaintext. Data throughput can be enhanced via pipelining while cost savings can be concurrently achieved as less wafer space and/or die area may be utilized. Adaptations may be made based upon a resulting complexity of implementing a particular design while satisfying a maximum throughput requirement.

Abstract: The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, a memory system, and a security system. The security system is adapted to selectively perform security processing on incoming and outgoing data. The security system comprises a key buffer and a pipeline. The pipeline performs an algorithm for encryption, decryption, or authentication according to the current key in the key buffer. The security system generates a signal after the last data block of a frame has been associated with a copy of the current key and, in response to the signal, advances the current key in the key buffer to the key for the next frame. The pipeline can thereby process data blocks from two different frames at one time, even where the data blocks use different keys.

Abstract: A digital differential analyzer (DDA) with parallel processing paths. The parallel processing paths can be provided through the use of a pipeline in which some of the input data registers are implemented with double buffers. Each double buffer includes an external register that corresponds to a setup path and an internal register that corresponds to a render path. While the rendering phase is being performed for the current primitive using the internal registers, the setup phase for the next primitive can be performed and the external registers can be updated. The two paths are synchronized with a prepare-to-render message. The DDA can include multiple arithmetic units to allow concurrent processing of multiple fragments of an object. The elements within the DDA (e.g., the internal registers, multiplexers, output registers, and so on) can be configured to provide more efficient implementations of scan conversion and subpixel correction than those of conventional DDAs.