Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.

Abstract: Disclosed herein are systems and techniques for general purpose input/output (GPIO)-to-GPIO communication in a multi-node, daisy-chained network. In some embodiments, a transceiver may support GPIO between multiple nodes, without host intervention after initial programming. In some such embodiments, the host may be required only for initial setup of the virtual ports. In some embodiments, GPIO pins can be inputs (which may change virtual ports) or outputs (which may reflect virtual ports). In some embodiments, multiple virtual ports may be mapped to one GPIO output pin (with the values OR'ed together, for example). In some embodiments, multiple GPIO input pins may be mapped to one virtual port. For example, multiple GPIO input pin values may be OR'ed together, even if they come from multiple nodes.

Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

Abstract: A workspace system includes different base components, different accessory interfaces and different accessories. Different accessory interfaces may be fixed to different base components, and different accessories may be releasably engaged by different, or the same accessory interfaces. The same accessories may be engaged by different accessory interfaces. The base components and accessories may be reconfigured to define different workspaces. Methods of assembling and reconfiguring the workspaces are also provided.

Abstract: There is provided a content automation system and a method for use by the content automation system for issuing a content management message for use in a program stream. In one implementation, such a content automation system comprises a processor and a memory, and a stream messaging module residing in the memory. The stream messaging module is configured to issue the content management message by embedding a command sequence as metadata in a container data structure, and inserting the container data structure into the program stream. The command sequence authorizes a replacement of program stream content.

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

Abstract: Disclosed herein are systems and techniques for slave-to-slave communication in a multi-node, daisy-chained network. Slave nodes may provide or receive upstream or downstream data directly to/from other slave nodes, without the need for data slots first to route through the master node.

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

Abstract: Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.

Abstract: There is provided a content automation system and a method for use by the content automation system for issuing a content management message for use in a program stream. In one implementation, such a content automation system comprises a processor and a memory, and a stream messaging module residing in the memory. The stream messaging module is configured to issue the content management message by embedding a command sequence as metadata in a container data structure, and inserting the container data structure into the program stream. The command sequence authorizes a replacement of program stream content.

Abstract: There is provided a content automation system and a method for use by the content automation system for issuing a content management message for use in a program stream. In one implementation, such a content automation system comprises a processor and a memory, and a stream messaging module residing in the memory. The stream messaging module is configured to issue the content management message by embedding a command sequence as metadata in a container data structure, and inserting the container data structure into the program stream. The command sequence authorizes a replacement of program stream content.

Abstract: Disclosed herein are systems and techniques for slave-to-slave communication in a multi-node, daisy-chained network. Slave nodes may provide or receive upstream or downstream data directly to/from other slave nodes, without the need for data slots first to route through the master node.

Abstract: Disclosed herein are systems and techniques for general purpose input/output (GPIO)-to-GPIO communication in a multi-node, daisy-chained network. In some embodiments, a transceiver may support GPIO between multiple nodes, without host intervention after initial programming. In some such embodiments, the host may be required only for initial setup of the virtual ports. In some embodiments, GPIO pins can be inputs (which may change virtual ports) or outputs (which may reflect virtual ports). In some embodiments, multiple virtual ports may be mapped to one GPIO output pin (with the values OR'ed together, for example). In some embodiments, multiple GPIO input pins may be mapped to one virtual port. For example, multiple GPIO input pin values may be OR'ed together, even if they come from multiple nodes.

Abstract: Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.

Abstract: In an example embodiment, a two-wire communication protocol engine manages control and data transmissions in a bi-directional, multi-node bus system where each node is connected over a twisted wire pair bus to another node. Some embodiments include a state machine that allows for synchronized updates of configuration data across the system, a distributed interrupt system, a synchronization pattern based on data coding used in the system, and data scrambling applied to a portion of the data transmitted over the twisted wire pair bus. The multi-node bus system comprises a master node and a plurality of slave nodes. The slave nodes can be powered over the twisted wire pair bus.

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

Abstract: In an example embodiment, a signal processor is disclosed that is configured to decode a clock-first, change-on-zero differential Manchester encoded data stream. The data stream has no local clock, and both combinatorial and sequential logic is used to decode the stream into a clocked data signal and an optional error signal. Decoding comprises a parser that separates the input data stream into an intermediate data signal, an intermediate clock signal, and a conditioning signal. A data and error generator receives the three signals and outputs a clocked data signal and a clocked error signal.

Abstract: In an example embodiment, a signal processor is disclosed that is configured to decode a clock-first, change-on-zero differential Manchester encoded data stream. The data stream has no local clock, and both combinatorial and sequential logic is used to decode the stream into a clocked data signal and an optional error signal. Decoding comprises a parser that separates the input data stream into an intermediate data signal, an intermediate clock signal, and a conditioning signal. A data and error generator receives the three signals and outputs a clocked data signal and a clocked error signal.