Abstract: The present disclosure provides systems and methods relating to neuromodulation. In particular, the present disclosure provides systems and methods for minimally invasive, targeted, vagus nerve stimulation (pVNS), and the efficacy of this approach with respect to microglial activation and the amelioration of cognitive dysfunction. The systems and methods of neuromodulation disclosed herein can be used to facilitate the treatment of various diseases associated with pathological neural activity.

Abstract: The present disclosure provides systems and methods relating to neuromodulation. In particular, the present disclosure provides systems and methods for minimally invasive, targeted, vagus nerve stimulation (pVNS), and the efficacy of this approach with respect to microglial activation and the amelioration of cognitive dysfunction. The systems and methods of neuromodulation disclosed herein can be used to facilitate the treatment of various diseases associated with pathological neural activity.

Abstract: The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register.

Abstract: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.

Abstract: Compounds are disclosed which are Fab I inhibitors and are useful in the treatment bacterial infections.