Abstract: Verification operations are utilized to effectively verify multiple associated write operations. A verification operation may be initiated after the issuance of a plurality of write operations that initiate the storage of data to a memory storage device, and may be configured to verify only a subset of the data written to the memory storage device by the plurality of write operations. As a result, verification operations are not required to be performed after each write operation, and consequently, the number of verification operations, and thus the processing and communication bandwidth consumed thereby, can be substantially reduced.

Abstract: A method and structure are provided for implementing enhanced cooling of a plurality of memory devices. The memory structure includes a stack of platters. A sub-plurality of memory devices is mounted on each platter. At least one connector is provided with each platter for connecting to the sub-plurality of memory devices. A heat sink is associated with the stack of platters for cooling the plurality of memory devices.

Abstract: A method and apparatus are provided for implementing a redundancy enhanced differential signal interface. A differential signaling I/O pair is coupled to a differential receiver interface. The differential receiver interface includes a pair of multiplexers coupled to a differential receiver. An error detecting mechanism is coupled to the differential receiver for detecting an error. When an error is detected, an interface operating speed is reduced. True and complement sides of a differential signaling I/O pair are alternately tested by first enabling a multiplexer control of one of the multiplexers, reading data, and checking for the error; then enabling a multiplexer control of the other multiplexer, reading data, and checking for the error. Responsive to detecting a failure of a true side or a complement side, the detected failed true side or complement side is set to a reference voltage and the reduced interface operating speed is maintained for continued operation.

Abstract: A method and apparatus are provided for detecting degradation, such as, array degradation and logic degradation, in integrated circuits (ICs) including application specific integrated circuits (ASICs). A monitor built-in self-test (MBIST) engine coupled to at least one monitor element that is defined by predefined circuit elements in the integrated circuit. The MBIST engine is used for controlling operation of at least one monitor element for communicating with monitor bits to identify degradation of signal, timing and voltage margins.

Abstract: Redundant capacity in a memory system is utilized to facilitate active monitoring of solid state memory devices in the memory system. All or part of the data stored in an active solid state memory device, and used in an active data processing system, may be copied to at least one redundant memory device, e.g., by transitioning a memory address range that was allocated to the active memory device to the redundant memory device. By doing so, memory access requests for the memory address range, which would normally be directed to the active memory device, may instead be directed to the redundant memory device, thus enabling the active memory device to be tested (e.g., via writing and reading test data patterns to the active memory device) without interrupting system access to that memory address range.

Abstract: A method, apparatus, and computer program product are provided for implementing an enhanced DRAM interface checking. An interface check mode enables interface checking using a refresh command for a DRAM. A predefined address pattern is provided for the interface address inputs during a refresh command cycle. Interface address inputs are checked for a proper value being applied and an error is signaled for unexpected results. An extended test mode includes further testing during a cycle after the refresh command cycle. Then command inputs also are checked for a proper value being applied and an error is signaled for unexpected results.

Abstract: Methods and apparatus are disclosed for use in an electronic system where data is transmitted over signaling conductors from one electronic component to another using strobe signals accompanying the data. The edge or transition of the strobe signals identifies when, in a window of time, the receiving electronic component should latch the data. In many such systems, data is transmitted over the signaling conductors in the form of a plurality “beats”, of data, proper timing to latch each beat of data being identified by a transition of the strobe signal. Faults in components or errors in transmission must be handled. The present invention discloses apparatus and methods to communicate conditions relevant to data transmitted without requiring additional signaling conductors. The present invention discloses selecting a message from a plurality of messages, encoding the selected message, and transmitting the encoded message on existing strobe lines to communicate the condition encountered.

Abstract: Methods and apparatus are disclosed for use in an electronic system where data is transmitted over signaling conductors from one electronic component to another using strobe signals accompanying the data. The edge or transition of the strobe signals identifies when, in a window of time, the receiving electronic component should latch the data. In many such systems, data is transmitted over the signaling conductors in the form of a plurality “beats”, of data, proper timing to latch each beat of data being identified by a transition of the strobe signal. Faults in components or errors in transmission must be handled. The present invention discloses apparatus and methods to communicate conditions relevant to data transmitted without requiring additional signaling conductors. The present invention discloses selecting a message from a plurality of messages, encoding the selected message, and transmitting the encoded message on existing strobe lines to communicate the condition encountered.

Abstract: An electrical connector includes a housing having a slot formed therein. The electrical connector further includes a plurality of conductive contact bands disposed within the slot. Each of the contact bands has a surface with a roughness defined by a plurality of microscopic irregularities. Each of the contact bands additionally has a plurality of projections, each of which projects above the surface of the contact band by a distance equal to a value between about 0.1% and 99% of a width of the contact band. The projections of each contact band electrically engage, at a plurality of different locations, with a conductive member insertable into the slot.