Patents by Inventor William Huott
William Huott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10998075Abstract: A non-limiting example includes data storage circuitry. The data storage circuitry includes a built-in self-test (BIST) engine. The data storage circuitry includes a memory array including memory cells. The memory array is configured to store data based on a read-write vector associated with an address vector that includes memory addresses and according to a bit-write vector that defines bit-write enablement for the memory addresses. The memory array is configured to output a stored data vector. The data storage circuitry includes a selector configured to receive the bit-write vector, and to output a selected vector based on an initialization vector and a comparison vector based at least in part on the bit-write vector. The data storage circuitry includes a comparator configured to receive the stored data vector and the selected vector, and to output an error based on discrepancies between the stored data vector and the selected vector.Type: GrantFiled: September 11, 2019Date of Patent: May 4, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William Huott, Daniel Rodko, Pradip Patel, Matthew Steven Hyde
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Patent number: 10971242Abstract: Embodiments of the present invention are directed to methods, systems, and circuitry for memory arrays. A system for testing a memory array having self-test circuitry includes a register having register latches operable to receive error logic signals having respective first states or second states. The register latches are arranged in series having respective latch inputs cascaded with preceding latch outputs operable to shift the error logic signals to a serial output according to a control signal that is common to the register latches. The system includes an aggregate latch operable to receive the serial output and having input logic configured to maintain a first state of the aggregate latch until the serial output is a second state. The system includes a built-in self-test (BIST) engine including stored instructions operable upon execution by the BIST engine to output the control signal.Type: GrantFiled: September 11, 2019Date of Patent: April 6, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William Huott, Daniel Rodko, Pradip Patel
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Publication number: 20210074376Abstract: A non-limiting example includes data storage circuitry. The data storage circuitry includes a built-in self-test (BIST) engine. The data storage circuitry includes a memory array including memory cells. The memory array is configured to store data based on a read-write vector associated with an address vector that includes memory addresses and according to a bit-write vector that defines bit-write enablement for the memory addresses. The memory array is configured to output a stored data vector. The data storage circuitry includes a selector configured to receive the bit-write vector, and to output a selected vector based on an initialization vector and a comparison vector based at least in part on the bit-write vector. The data storage circuitry includes a comparator configured to receive the stored data vector and the selected vector, and to output an error based on discrepancies between the stored data vector and the selected vector.Type: ApplicationFiled: September 11, 2019Publication date: March 11, 2021Inventors: William Huott, Daniel Rodko, Pradip Patel, Matthew Steven Hyde
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Publication number: 20210074375Abstract: Embodiments of the present invention are directed to methods, systems, and circuitry for memory arrays. A system for testing a memory array having self-test circuitry includes a register having register latches operable to receive error logic signals having respective first states or second states. The register latches are arranged in series having respective latch inputs cascaded with preceding latch outputs operable to shift the error logic signals to a serial output according to a control signal that is common to the register latches. The system includes an aggregate latch operable to receive the serial output and having input logic configured to maintain a first state of the aggregate latch until the serial output is a second state. The system includes a built-in self-test (BIST) engine including stored instructions operable upon execution by the BIST engine to output the control signal.Type: ApplicationFiled: September 11, 2019Publication date: March 11, 2021Inventors: William Huott, Daniel Rodko, Pradip Patel
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Patent number: 10890623Abstract: Techniques for a power saving scannable latch output driver in an integrated circuit (IC) are described herein. An aspect includes receiving, by a circuit comprising a scannable latch, a scan signal. Another aspect includes, based on the scan signal being enabled, turning on a scan output driver of the scannable latch, wherein a scan input of the scannable latch propagates through the scannable latch to a scan output based on the scan output driver being turned on. Another aspect includes, based on the scan signal being disabled, turning off the scan output driver, wherein the scan output driver comprises a first p-type field effect transistor (PFET) and a first n-type field effect transistor (NFET), wherein a gate of the first PFET and a gate of the first NFET are connected to an output of a latch of the scannable latch.Type: GrantFiled: September 4, 2019Date of Patent: January 12, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William Huott, Yuen Chan, Pradip Patel, Daniel Rodko
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Publication number: 20080098268Abstract: In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.Type: ApplicationFiled: October 31, 2007Publication date: April 24, 2008Inventors: Leendert Huisman, William Huott, Franco Motika, Leah Pfeifer Pastel
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Publication number: 20080059854Abstract: The output register of an array and the Multiple Input Signature Register (MISR) logic is implemented with one set of L1/L2 master/slave latches and single additional slave latch. This new combined logic uses less critical area on a chip without a performance impact on the array access time or circuit testing.Type: ApplicationFiled: October 22, 2007Publication date: March 6, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yuen Chan, William Huott, Pradip Patel, Daniel Rodko
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Publication number: 20080059857Abstract: Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the scan chain in a second test mode. A portion of the scan chain adjacent and following a stuck-@-0 or stuck-@-1 fault in the scan chain may store and/or output a value complementary to the value on the output of the previous portion of the scan chain due to the fault. Such values may be unloaded from the scan chain and used for diagnosing (e.g., isolating a defect in) the defective scan chain. Numerous other aspects are provided.Type: ApplicationFiled: October 25, 2007Publication date: March 6, 2008Inventors: LEENDERT HUISMAN, William Huott, Maroun Kassab, Franco Motika
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Publication number: 20080030246Abstract: Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal. A local pass gate receives the clock low signal and the clock high signal and generating an (n+0.5)-to-1 clock signal in response to at least one of the global clock signal, the clock high signal and the clock low signal.Type: ApplicationFiled: October 10, 2007Publication date: February 7, 2008Applicant: INTERNATIONAL BUSINES MACHINE CORPORATIONInventors: William Huott, Charlie Hwang, Timothy McNamara
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Publication number: 20070176651Abstract: Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal, the clock high signal and the clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high signal and the clock low signals have patterns that match the targeted divided clock frequency and duty cycle. A local pass gate receives the clock low signal and the clock high signal and generates an (n+0.5)-to?1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.Type: ApplicationFiled: January 27, 2006Publication date: August 2, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William Huott, Charlie Hwang, Timothy McNamara
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Publication number: 20070176652Abstract: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the centralized state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal, the clock high and clock low signal having patterns derived from a waveform of a target divided ratio clock and the clock high and clock low signals have patterns that match the targeted divided clock frequency and duty cycle. Local pass gate are provided for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.Type: ApplicationFiled: January 27, 2006Publication date: August 2, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William Huott, Charlie Hwang, Timothy McNamara
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Publication number: 20070176653Abstract: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.Type: ApplicationFiled: May 19, 2006Publication date: August 2, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William Huott, Charlie Hwang, Timothy McNamara
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Publication number: 20070165445Abstract: An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.Type: ApplicationFiled: January 18, 2006Publication date: July 19, 2007Applicant: International Business Machines CorporationInventors: Yuen Chan, William Huott, Donald Plass
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Publication number: 20060242506Abstract: This invention describes a method of synchronizing test clocks in an LSSD system to achieve near simultaneous arrival of the clock signals at the inputs of all LSSD registers. The method relies on pipelining the latches to distribute the test clocks, where all pipeline latches are synchronized by the system clock. This enhancement improves the frequency at which the test clocks switch and improve the testing throughput by reducing testing time, resulting in significant reductions in testing hardware and overall time required for system test, without compromising any of the benefits associated with conventional LSSD techniques. The method further enhances the distribution of the test clock signals to points throughout the entire chip, with a distribution network that is tailored according to a desired LBIST speed.Type: ApplicationFiled: April 25, 2005Publication date: October 26, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Warnock, William Huott
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Publication number: 20060203578Abstract: An apparatus and method for protecting a computer system from array reliability failures uses Array Built-In Self-Test logic along with code and hardware to delete cache lines or sets that are defective, identify corresponding fuse repair values, proactively call home if spare fuses are not available, schedule soft fuse repairs for the next system restart, schedule line deletes at the next restart, store delete and fuse repairs in a table (tagged with electronic serial id, timestamp of delete or ABIST fail event, address, and type of failure) and proactively call home if there were any missed deletes that were not logged. Fuse information can also be more permanently stored into hardware electronic fuses and/or EPROMs. During a restart, previous repairs are able to be applied to the machine so that ABIST will run successfully and previous deletes to be maintained with checking to allow some ABIST failures which are protected by the line deletes to pass.Type: ApplicationFiled: March 14, 2005Publication date: September 14, 2006Applicant: International Business Machines CorporationInventors: Patrick Meaney, William Huott, Thomas Knips, David Lund, Bryan Mechtly, Pradip Patel
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Publication number: 20060195740Abstract: An output of an element under test is captured and stored, through a multiplexer, in a capture register. At a clock edge (either rising or falling edge) the element under test catches the “edge” and “strobes” the output. The multiplexer is strobed, and the delay and duty cycle are measured. Both the rising and falling edge are used as the timer.Type: ApplicationFiled: February 11, 2005Publication date: August 31, 2006Applicant: International Business Machines CorporationInventors: William Huott, Pradip Patel, Daniel Rodko
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Publication number: 20060195738Abstract: The output register of an array and the Multiple Input Signature Register (MISR) logic is implemented with one set of L1/L2 master/slave latches and single additional slave latch. This new combined logic uses less critical area on a chip without a performance impact on the array access time or circuit testing.Type: ApplicationFiled: February 11, 2005Publication date: August 31, 2006Applicant: International Business Machines CorporationInventors: Yuen Chan, William Huott, Pradip Patel, Daniel Rodko
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Publication number: 20060195288Abstract: A method of and system for testing multi clock domain devices at functional clock speed by aligning the Launching C2 clocks of the high speed and low speed domains, issuing a Cl->C2 clock in each domain, to at speed test all intra-domain paths and the low speed to high speed paths; aligning the capturing C1 clock edges of the high speed and low speed clocks; and issuing a C2->C1 clock in each domain, to test the high speed to low speed paths.Type: ApplicationFiled: February 12, 2005Publication date: August 31, 2006Inventors: Timothy McNamara, Joseph Eckelman, William Huott
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Publication number: 20060181941Abstract: Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.Type: ApplicationFiled: February 11, 2005Publication date: August 17, 2006Applicant: International Business Machines CorporationInventors: Tom Chang, William Huott, Thomas Knips, Donald Plass
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Publication number: 20060181326Abstract: A system for locally generating a ratio clock from a global clock based on a global clock gate signal includes a staging unit, a pass gate, and a state machine. The state machine is electrically connected to an output of the staging unit and an input of the pass gate. The state machine includes state elements and associated logic. The associated logic is configured to allow said state elements to pass through a number of logic states for every same number of consecutive edges of the global clock when the associated logic is enabled. The number is a positive integer.Type: ApplicationFiled: February 11, 2005Publication date: August 17, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William Huott, Timothy McNamara