Abstract: A thick glass passivation layer comprises an alternating sequence of structurally dissimilar but chemically compatible layers of material over the surface of a substrate, so as to provide sufficient elasticity to compensate for thermal expansion differences that would otherwise crack causing in thick monolithic films. A first layer comprises glass that has been deposited over the surface of the structure using chemical vapor deposition. A second layer of the passivating glass material is then provided on the substrate using a spinning technique. The chemical vapor deposition and spun layers continue to be applied in an alternating fashion until a film having the desired thickness is formed. Each chemical vapor deposition layer provides an elastic cushion for the subsequently spun layers. The spun layers allows a planar topography to be maintained without the need for high temperatures.

Abstract: A process is disclosed for forming a planarized or smooth surface binary glass insulating film comprised of germanium dioxide and silicon dioxide by a spin-on process. The resulting structure has a film thickness uniformity which varies less than 5% over the surface of the wafer. The structure is formed by mixing a predetermined solution of TEOS and TEOG in a lower alcohol or ketone solvent and catalyzing by the addition of sufficient acid to raise the pH to 1.5 to 2.0 to favor gel formation. The resultant solution is then spun on at an RPM selected to give the desired film thickness for a given solids content of the solution.

Abstract: An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape around said island to laterally define the dimensions of each such island, an oxide (12, 14) formed over the surface of said grooves (13-1 through 13-6) and said islands and a selected glass (15) deposited on said oxide (14) in the grooves and over the top surface of said device, said glass having the property that it flows at a temperature beneath the temperature at which dopants in the islands of semiconductor material substantially redistribute, said selected glass (15) having a substantially flat top surface thereby to give said structure a substantially flat top surface.

Abstract: A photomask for use in manufacturing integrated circuits is fabricated by coating a thin film of organic material, generally a solution of a thermally decomposable hydrocarbon, onto a glass plate and heating it in a reducing atmosphere to convert it into carbon. The carbon layer is masked and etched; for example, in an oxygen plasma, to produce the mask.

Abstract: There is disclosed herein a stress relieved intermediate insulating layer consisting of one or more layers of spun-on glass lying over a metalization pattern. The spun-on layers are allowed to crack from thermal stress imposed upon the structure. The cracks in the spun-on layers are then filled with a glass layer deposited by CVD or LPCVD.

Abstract: An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape around said island to laterally define the dimensions of each such island, an oxide (12, 14) formed over the surface of said grooves (13-1 through 13-6) and said islands and a selected glass (15) deposited on said oxide (14) in the grooves and over the top surface of said device, said glass having the property that it flows at a temperature beneath the temperature at which dopants in the islands of semiconductor material substantially redistribute, said selected glass (15) having a substantially flat top surface thereby to give said structure a substantially flat top surface.

Abstract: A method of introducing a controlled flow of vapor from a high pressure sublimation chamber into a low pressure vapor deposition reactor, said vapor being derived from solid source material preferably, but not necessarily, having a vapor pressure above about one (1) Torr at a temperature not exceeding about 350.degree. C. The method comprises controllably heating the source material to a temperature sufficient to produce vapor therefrom at a desired pressure, and then controllably transferring the vapor through vapor transmission means to the vapor deposition reactor. During such transfer, the transmission means is maintained at a temperature sufficient to prevent condensation of the vapor therein during transfer. The vapor is delivered to the reactor in a pure state and is not mixed with any carrier medium.

Abstract: A method for forming a substantially planar inorganic dielectric layer over a predetermined pattern of electrical interconnects comprises the steps of reacting phosphoric acid and a trivalent metallic halide compound with an aliphatic solvent to form a coating fluid. The coating fluid is then spun onto the semiconductor device to form a layer over the electrical interconnect. The resultant device is then baked at a first temperature to drive off the solvent and then baked at a second, higher temperature, in order to promote the glass forming reaction. This process is repeated as required to form a coating layer having a thickness which exhibits levelling characteristics of such high quality that fine topography can be carried out on succeeding layers of metal in order to form additional interconnect layers with precision.

Abstract: A low temperature insulating glass for use in semiconductor devices comprises a mixture of germanium, silicon, oxygen and phosphorus. In the preferred embodiment, the glass comprises a mixture of about 40% to 55% silicon dioxide (SiO.sub.2), about 55% to 40% of germanium dioxide (GeO.sub.2) and from 1% to about 5% of phosphorus pentoxide (P.sub.2 O.sub.5), by mole percent.

Abstract: A process and resulting structure are disclosed for forming vias in integrated circuit structures using metal silicide interconnections. A lower conductor is formed by sequentially depositing silicon and a refractory metal which reacts with the silicon to create a layer of metal silicide. A subsequent layer of silicon is deposited on the surface of the metal silicide. This layer of silicon is insulated from overlying layers by forming insulating material over desired regions of the layer of silicon. A second layer of metal is then deposited across the structure. In openings in the insulating material the metal reacts with the second layer of silicon to form a via of metal silicide. A final layer of silicon may be deposited to convert any remaining metal in the second layer of metal to metal silicide, and the structure annealed to lower its resistivity.

Abstract: An interconnect structure for use in integrated circuits comprises a germanium-silicon binary alloy. Such an alloy is deposited on the semiconductor wafer from the co-deposition of germanium and silicon using chemical vapor deposition techniques of a type commonly used in the semiconductor industry. The resulting alloy can be oxidized, selectively removed and doped with selected impurities to provide a conductive lead pattern of a desired shape on the surface of a wafer.

Abstract: In a semiconductor device, laser energy is used to selectively heat various SiO.sub.2 and/or GeO.sub.2 based materials to elevated temperatures while maintaining the active device region and electrical interconnects at relatively low temperatures, to for example, induce densification and/or flow of the SiO.sub.2 and/or GeO.sub.2 based material to round off sharp edges and stops, without damaging or affecting the active region and electrical interconnects.

Abstract: A novel process is disclosed for the selective etching of a protective layer over a substrate according to a predetermined pattern, which does not involve the use of chemical vapor deposition or vacuum techniques. The process incorporates the techniques of electroless metal deposition after first applying a mask which is positive with respect to the predetermined pattern. In alternative embodiments, the application to the masked protective layer of an agent catalytic to the reception of electroless metal deposition is followed by either immersion in an electroless plating bath and subsequent mask removal, or by mask removal and subsequent immersion in the electroless plating bath. In either embodiment, the protective layer is effectively masked and patterned for plasma etching. The process is useful in forming openings in the protective layer to permit selective doping of the underlying substrate.

Abstract: The method of the invention provides a thin film deposit of a binary glass for use in integrated circuits which binary glass has a softening or flow point far below temperatures at which glasses normally used in connection with integrated circuits flow. After the binary glass has been deposited (on a semiconductor substrate), it is heated and reflowed. Preferably the glass comprises a mixture of germanium dioxide and silicon dioxide wherein the germanium dioxide is no greater than approximately 50 mole percent of the mixture. Phosphorus is added to the glass film for passivation of the underlying devices.

Abstract: A process and resulting structure are disclosed for forming vias in integrated circuit structures using metal silicide interconnections. A lower conductor is formed by sequentially depositing silicon and a refractory metal which reacts with the silicon to create a layer of metal silicide. A subsequent layer of silicon is deposited on the surface of the metal silicide. This layer of silicon is insulated from overlying layers by forming insulating material over desired regions of the layer of silicon. A second layer of metal is then deposited across the structure. In openings in the insulating material the metal reacts with the second layer of silicon to form a via of metal silicide. A final layer of silicon may be deposited to convert any remaining metal in the second layer of metal to metal silicide, and the structure annealed to lower its resistivity.

Abstract: A method for forming a predetermined configuration of a film material comprises the steps of forming a layer of a first material on a surface, forming a layer of a second material on the first material wherein the first material has an etch rate greater than that of the second material when the first material and the second material are exposed to a common etchant, etching portions of the second material and underlying portions of the first material to expose portions of the surface, forming a layer of film material on the exposed portions of the surface, forming a layer of film material on the exposed portions of the surface and on the remaining portions of the second material, and removing the remaining portions of the first material such that the overlying second material and the film material thereon is also removed.

Abstract: A low temperature LPCVD process for co-depositing metal and silicon to form metal silicide on a surface such as the surface of a semiconductor integrated circuit wherein the metal is selected from the group consisting of tungsten, molybdenum, tantalum and niobium. A reactor which contains the surface is maintained at a temperature of about 500.degree.-700.degree. C. The reactor is purged by the successive steps of introducing an inert gas into the reactor, introducing a reducing atmosphere into the reactor and introducing hydrogen chloride gas into the reactor. Silane is then introduced into the reactor such that a base layer of polysilicon is formed on the surface. Then, while maintaining silane introduction to the reactor, metal chloride vapor is simultaneously introduced into the reactor such that metal and silicon are co-deposited on the polysilicon as metal silicide.

Abstract: A process for patterning regions on a semiconductor structure comprises the steps of forming a first layer of an alloy of tungsten and titanium on the semiconductor structure, forming a conductive layer of aluminum or chemically similar material on the surface of the tungsten-titanium alloy, removing the undesired portions of the conductive layer by etching with a plasma and removing the thereby exposed portions of the tungsten-titanium alloy layer by chemical etching.