Abstract: An automatic circuit tester (10) applies signals to tester terminals (12a, b, and c) by means of corresponding data channels (14a, b and c). Each channel includes a leading-edge memory 18 and a trailing-edge memory 20 that provide outputs of successive locations upon the occurrences of clock pulses applied by a clock 16 through respective phase shifters (22 and 24). A formatter (26) applies signals in accordance with the outputs of the memories (18 and 20) with a timing format determined directly by the times at which the memory outputs occur; no separate timing information is required by the formatters. The timing results from the phase shifts imposed by phase shifters 22 and 24 and by transitions in the contents of a plurality of successive memory locations provided for each period of the device under test.