Abstract: A pixel cell having a photosensor within a silicon substrate; and an oxide layer provided over the photosensor, the oxide layer having a grated interface with said silicon substrate, and a method of fabricating the pixel cell having a grated interface.

Abstract: A pixel cell having a photosensor within a silicon substrate; and an oxide layer provided over the photosensor, the oxide layer having a grated interface with said silicon substrate, and a method of fabricating the pixel cell having a grated interface.

Abstract: Reticles having reticle patterns suitable for reducing edge of array effects are provided. The reticle patterns have unresolvable patterns formed in the periphery areas of the reticle patterns. The unresolvable patterns are non-transparent with respect to patterning radiation. Systems incorporating the reticles are also provided. Additionally, methods of forming and using the reticles are provided.

Abstract: A semiconductor pattern mask that might otherwise exhibit three-fold symmetry, which could give rise to distorted semiconductor features in the presence of three-leaf aberration in the optical system used to expose a semiconductor wafer through the mask, is altered to break up the three-fold symmetry without altering the semiconductor features that are formed. This accomplished by adding features to the mask that break up the symmetry. One way of achieving that result is to make the added features of “sub-resolution” size that do not produce features on the exposed wafer. Another way of achieving that result is to change existing features that do form structures in such a way (e.g., with optical elements) that changes the relative phase, amplitude or other characteristic of light transmitted through those features.

Abstract: Reticles having reticle patterns suitable for reducing edge of array effects are provided. The reticle patterns may have sub-resolution patterns or a transmissive block fill formed in the periphery areas of the reticle patterns. Systems incorporating the reticles are also provided. Additionally, methods of forming and using the reticles are provided.

Abstract: A semiconductor pattern mask that might otherwise exhibit three-fold symmetry, which could give rise to distorted semiconductor features in the presence of three-leaf aberration in the optical system used to expose a semiconductor wafer through the mask, is altered to break up the three-fold symmetry without altering the semiconductor features that are formed. This accomplished by adding features to the mask that break up the symmetry. One way of achieving that result is to make the added features of “sub-resolution” size that do not produce features on the exposed wafer. Another way of achieving that result is to change existing features that do form structures in such a way (e.g., with optical elements) that changes the relative phase, amplitude or other characteristic of light transmitted through those features.

Abstract: Reticles having reticle patterns suitable for reducing edge of array effects are provided. The reticle patterns may have sub-resolution patterns or a transmissive block fill formed in the periphery areas of the reticle patterns. Systems incorporating the reticles are also provided. Additionally, methods of forming and using the reticles are provided. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that is will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: A semiconductor pattern mask that might otherwise exhibit three-fold symmetry, which could give rise to distorted semiconductor features in the presence of three-leaf aberration in the optical system used to expose a semiconductor wafer through the mask, is altered to break up the three-fold symmetry without altering the semiconductor features that are formed. This accomplished by adding features to the mask that break up the symmetry. One way of achieving that result is to make the added features of “sub-resolution” size that do not produce features on the exposed wafer. Another way of achieving that result is to change existing features that do form structures in such a way (e.g., with optical elements) that changes the relative phase, amplitude or other characteristic of light transmitted through those features.

Abstract: A computer implemented method that uses a full integrated circuit (IC) chip design, to be printed by an attenuated phase shift mask, as an input parameter. Each feature environment within the input full IC chip design is individually simulated to determine how the features within the environment would be printed from the mask created according to the input design. The simulation of each environment also determines the extent and locations of unwanted side lobes that would also be printed from the mask. Once the side lobes are determined, auxiliary features are incorporated into the input design so that the auxiliary features will become transparent openings within a mask created in accordance with the modified input design. Each auxiliary feature opening is placed at a side lobe location and is designed to eliminate the side lobe by passing radiant energy that is 180 degrees out of phase with the radiant energy of the side lobe.