Abstract: Method, system, computer, etc., embodiments receive an original integrated circuit design into a computerized device. The methods herein automatically replace at least some of the original cells within the original integrated circuit design with replacement cells using the computerized device. Each of the replacement cells has an initial cell size that is unassociated with any specific design size. The methods herein automatically change the original design size of the integrated circuit design to a changed design size, and automatically individually change the initial cell size of each of the replacement cells to different sizes. At least two different replacement cells are changed from the initial cell size by different size reduction amounts based on different amounts of space required within the changed design size for each of the replacement cells.

Abstract: A charge pumping structure is disclosed for use in a substrate bias voltage generator. It includes a capacitor on a substrate region for coupling to a first node periodic voltage signals received at a second node. A first diode structure provides a current path from the first node to the substrate and a second diode structure provides a current path between the first node and a reference potential, which is typically the ground. The first diode structure includes a PN junction diode, an isolation ring for collecting minority charge carriers injected into the substrate and is constructed on a portion of the substrate that has a lower doping concentration than the underlying substrate portion establishing a built-in electric field which inhibits the flow of minority carriers from the first diode to the underlying substrate.

Abstract: Disclosed is an overvoltage protection structure which when used with CMOS circuits it protects them from overvoltage conditions while minimizing latch-up conditions in the structure. It consists of a well region of an opposite conductivity to that of the substrate defining a pocket region having a conductivity type which is similar to that of the substrate. A first PN junction diode is formed in a portion of the well region and a second PN junction diode is formed in the pocket region. The two diodes have opposite polarity and they both are connected to a signal line in such a way that one of the two diodes will be forward biased if the voltage on the signal line exceeds the bounds of the power supply voltages. The pocket region is connected to a V.sub.SS terminal which is normally grounded and the well region is connected to a power supply V.sub.DD.