Patents by Inventor William J. Davis
William J. Davis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240143350Abstract: A system for generating a user interface described herein can include a processor to detect a type of the system based on hardware components residing within the system or coupled to the system and determine a user interface manager to execute based on the type of the system. The processor can also execute the user interface manager to generate a user interface for the system, wherein the type of the user interface manager comprises a plurality of rules to indicate a layout of the user interface.Type: ApplicationFiled: September 8, 2023Publication date: May 2, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Ramrajprabu BALASUBRAMANIAN, Darren R. DAVIS, Kenton A. SHIPLEY, Nathan T. RADEBAUGH, Paul DYKSTRA, Jan Harold KARACHALE, Brian David CROSS, Patrick J. DERKS, William Scott STAUBER, Nishad MULYE
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Publication number: 20230207497Abstract: An interconnect layer for an integrated circuit device includes a low radio frequency (RF) loss primary coating that forms a main portion of the interconnect layer, an opening formed in the primary coating, a high aspect ratio patternable secondary coating within the opening, and a via formed in the secondary coating. An aspect ratio of the via is greater than an aspect ratio of the opening.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Jarrod N. Vaillancourt, William J. Davis
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Patent number: 10420414Abstract: A belt and neck holder for a container such as a can of paint which offsets the container from the wearer via a double axis gimbal mechanism to provide free axial rotation of the secured container to prevent spillage. The holder is detachable from the belt and neck and provided in different sizes to hold standard containers such as a gallon can of paint.Type: GrantFiled: January 8, 2018Date of Patent: September 24, 2019Inventors: Robert L. Snyder, Randy Newman, Larry Lambert, William J. Davis
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Patent number: 9219000Abstract: Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.Type: GrantFiled: March 26, 2014Date of Patent: December 22, 2015Assignee: RAYTHEON COMPANYInventors: Paul J. Duval, Kamal Tabatabaie, William J. Davis
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Patent number: 8987892Abstract: A method for forming cooling channels in an interface for soldering to a semiconductor structure. The method includes: forming a metal seed layer on a surface of a substrate; patterning the metal seed layer into a patterned, plating seed layer covering portions of the substrate and exposing other portions of the substrate; using the patterned plating seed layer to form channels through the exposed portions of the substrate; and plating the patterned plating seed layer with solder. A heat exchanger having cooling channels therein is affixed to one surface of the interface and the semiconductor structure is soldered to an opposite surface of the interface. The cooling channels of the heat exchanger are aligned with the channels in the interface.Type: GrantFiled: May 10, 2013Date of Patent: March 24, 2015Assignee: Raytheon CompanyInventors: William J. Davis, David H. Altman
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Patent number: 8969176Abstract: A package for a plurality of semiconductor devices having: an electrical interconnect structure, comprising: an electrical interconnect structure; and an active device structure, comprising the plurality of semiconductor devices on an active device substrate. The electrical interconnect structure is bonded to the active device structure and the electrical interconnect structure provides electrical interconnection among the semiconductor devices.Type: GrantFiled: December 3, 2010Date of Patent: March 3, 2015Assignee: Raytheon CompanyInventors: Ward G. Fillmore, William J. Davis
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Publication number: 20140332949Abstract: A method for forming cooling channels in an interface for soldering to a semiconductor structure. The method includes: forming a metal seed layer on a surface of a substrate; patterning the metal seed layer into a patterned, plating seed layer covering portions of the substrate and exposing other portions of the substrate; using the patterned plating seed layer to form channels through the exposed portions of the substrate; and plating the patterned plating seed layer with solder. A heat exchanger haying cooling channels therein is affixed to one surface of the interface and the semiconductor structure is soldered to an opposite surface of the interface. The cooling channels of the heat exchanger are aligned with the channels in the interface.Type: ApplicationFiled: May 10, 2013Publication date: November 13, 2014Applicant: Raytheon CompanyInventor: William J. Davis
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Publication number: 20140206173Abstract: Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.Type: ApplicationFiled: March 26, 2014Publication date: July 24, 2014Applicant: RAYTHEON COMPANYInventors: Paul J. Duval, Kamal Tabatabaie, William J. Davis
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Patent number: 8754421Abstract: Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.Type: GrantFiled: February 24, 2012Date of Patent: June 17, 2014Assignee: Raytheon CompanyInventors: Paul J. Duval, Kamal Tabatabaie, William J. Davis
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Patent number: 8653673Abstract: A package and method for packaging a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices.Type: GrantFiled: December 20, 2011Date of Patent: February 18, 2014Assignee: Raytheon CompanyInventors: Robert B. Hallock, William J. Davis, Yiwen Zhang, Ward G. Fillmore, Susan C. Trulli, Jason G. Milne
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Patent number: 8581406Abstract: A MMIC flip chip mounted to a circuit board having an underfill material disposed between the MMIC and the circuit board and a barrier structure for preventing the underfill material from being disposed under an electronic device of the MMIC while providing a cavity under the electronic device.Type: GrantFiled: April 20, 2012Date of Patent: November 12, 2013Assignee: Raytheon CompanyInventors: James A. Robbins, William J. Davis, Robert B. Hallock
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Publication number: 20130277843Abstract: A MMIC flip chip mounted to a circuit board having an underfill material disposed between the MMIC and the circuit board and a barrier structure for preventing the underfill material from being disposed under an electronic device of the MMIC while providing a cavity under the electronic device.Type: ApplicationFiled: April 20, 2012Publication date: October 24, 2013Applicant: Raytheon CompanyInventors: James A. Robbins, William J. Davis, Robert B. Hallock
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Patent number: 8542720Abstract: Improvements in the detection of TWACS outbound message signals. A first improvement involves matching some (or all) of the intermediate points in an outbound preamble occurring between bits of the preamble currently being detected. This reduces the possibility of a false synchronization and therefore decreases the probability of missing outbound message signals. A second improvement is to require some or all of the known preamble bits to exceed a predetermined threshold where both the thresh-old and which bits are adjustable. An additional approach is using 4-8 additional buffers in a transponder to detect preamble patterns in the outbound message. Each half cycle of the outbound message waveform requires entering a bit only into the buffers active for the particular frame of reference in which the message is being transmitted, since only buffers for that frame of reference are employed. The process continues until all bits specified to be sent, based on the length of the outbound message, are extracted.Type: GrantFiled: April 18, 2008Date of Patent: September 24, 2013Assignee: Aclara Power-Line Systems, Inc.Inventors: Quentin H. Spencer, John B. Hessling, Jr., Benjamin A. Hammond, Dennis L. Kelley, David W. Rieken, William J. Davis, Michael R. Walker, II
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Publication number: 20130221365Abstract: Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.Type: ApplicationFiled: February 24, 2012Publication date: August 29, 2013Applicant: Raytheon CompanyInventors: Paul J. Duval, Kamal Tabatabaie, William J. Davis
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Publication number: 20130154124Abstract: A package and method for packaging a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices.Type: ApplicationFiled: December 20, 2011Publication date: June 20, 2013Applicant: Raytheon CompanyInventors: Robert B. Hallock, William J. Davis, Yiwen Zhang, Ward G. Fillmore, Susan C. Trulli, Jason G. Milne
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Publication number: 20120139100Abstract: A package for a plurality of semiconductor devices having: an electrical interconnect structure, comprising: an electrical interconnect structure; and an active device structure, comprising the plurality of semiconductor devices on an active device substrate. The electrical interconnect structure is bonded to the active device structure and the electrical interconnect structure provides electrical interconnection among the semiconductor devices.Type: ApplicationFiled: December 3, 2010Publication date: June 7, 2012Applicant: Raytheon CompanyInventors: Ward G. Fillmore, William J. Davis
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Patent number: 8178391Abstract: A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming, in a first lithographically processable material disposed on the surface portion of the semiconductor wafer, device exposing openings to expose the devices and electrical contact pad openings to expose electrical contact pads for devices; and mounting a support having a rigid dielectric layer formed on a selected portion of the support, such rigid dielectric layer comprising a second lithographically processable material, such rigid material being suspended over the device exposing openings and removed from portions of the support disposed over the electrical contacts pads openings in the first lithographically processable material. The support is released and removed from the second lithographically processable material, leaving the second photolithographically processable material bonded to the first photolithographically processable material.Type: GrantFiled: September 23, 2011Date of Patent: May 15, 2012Assignee: Raytheon CompanyInventors: William J. Davis, Ward G. Fillmore, Scott MacDonald
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Patent number: D666910Type: GrantFiled: May 27, 2011Date of Patent: September 11, 2012Assignee: Tropicana Products, Inc.Inventors: Asit Modha, William J. Davis, David J. McNeill
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Patent number: D666911Type: GrantFiled: July 29, 2011Date of Patent: September 11, 2012Assignee: Tropicana Products, Inc.Inventors: Asit Modha, William J. Davis, David J. McNeill
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Patent number: D725345Type: GrantFiled: March 10, 2014Date of Patent: March 31, 2015Assignee: Sivad Sleeve Aide LLCInventor: William J. Davis