Abstract: The present disclosure is directed to numerical test data reporting using an image file and subsequent analysis of the test data. A method for capturing and analyzing test data in accordance with an embodiment includes: capturing multi-bit integer values of test data; writing each multi-bit integer value to a multi-bit vertical field in an image file; extracting the multi-bit integer values from the multi-bit vertical fields in the image file; and analyzing the extracted multi-bit integer values.

Abstract: Reporting and/or analyzing test data from a plurality of tests of an array structure using a data array. One method includes obtaining the test data, and reporting the test data in a data array, which includes at least two portions representing different tests. Data stored in the data array is organized according to a translation table, which describes the locations of data for tests and criteria for data to be analyzed within the data array. Numerous other data arrangements such as a coordinate file listing a pre-defined maximum number of fail points, or a chip report including fail points by chip may also be generated. The data array reports all test data in a more easily generated and stored form, and may be converted to an image. A data analysis method for analyzing data using the data array is also presented.

Abstract: The present disclosure is directed to numerical test data reporting using an image file and subsequent analysis of the test data. A method for capturing and analyzing test data in accordance with an embodiment includes: capturing multi-bit integer values of test data; writing each multi-bit integer value to a multi-bit vertical field in an image file; extracting the multi-bit integer values from the multi-bit vertical fields in the image file; and analyzing the extracted multi-bit integer values.

Abstract: An on-chip temperature control system includes a temperature sensor, which monitors a temperature of a chip, and a hysteresis comparator which checks whether the temperature is in an acceptable range. A reference adjustment circuit is responsive to the hysteresis comparator to adjust an on-chip voltage to control the temperature locally by adjusting a local supply voltage, if the temperature is out of range.

Abstract: A structure and method are provided for forming a thermistor. Isolation structures are formed in a substrate including at least an upper layer of a single crystal semiconductor. A layer of salicide precursor is deposited over the isolation region and the upper layer. The salicide precursor is then reacted with the upper layer to form a salicide self-aligned to the upper layer. Finally, the unreacted portions of the salicide precursor are then removed while preserving a portion of the salicide precursor over the isolation region as a body of the thermistor. An alternative integrated circuit thermistor is formed from a region of thermistor material in an embossed region of an interlevel dielectric (ILD).