Abstract: A method and apparatus to create bypass logic in a digital circuit design comprising coupling a first latency delay unit to a data input of the conditional state element (e.g., a flip-flop). Coupling a second latency delay unit to an enable input of the conditional state element. Coupling a first input of a multiplexer to an output of the conditional state element. Coupling a second input of the multiplexer to the data input of the conditional state element; and coupling a select line of the multiplexer to the enable input of the conditional state element to form a logically redundant element. Replacing the conditional state element in a feedback loop of a finite state machine with the logically redundant element and manipulating latency delay units to create bypass logic in the digital circuit design.

Abstract: A method and apparatus to create bypass logic in a digital circuit design comprising coupling a first latency delay unit to a data input of the conditional state element (e.g., a flip-flop). Coupling a second latency delay unit to an enable input of the conditional state element. Coupling a first input of a multiplexer to an output of the conditional state element. Coupling a second input of the multiplexer to the data input of the conditional state element; and coupling a select line of the multiplexer to the enable input of the conditional state element to form a logically redundant element. Replacing the conditional state element in a feedback loop of a finite state machine with the logically redundant element and manipulating latency delay units to create bypass logic in the digital circuit design.

Abstract: A method of data compression for continuous or piecewise linear curves in two variables is presented which can guarantee that any compression error is exclusively on one selected side of the curve. Limiting errors to one side is required when simulating integrated circuit performance to determine if a design will have speed-related problems. In such a simulation it is necessary to calculate both the minimum and maximum possible time delays for a logic chain of circuit elements. Data compression of the transistor or gate voltage versus time relationship is necessary to reduce the very large amount of data that is required for the simulation. Data compression may introduce errors into the data in either direction. If it is necessary to have any possible error confined to one side of the curve, the compressed data must be shifted toward the desired error side by at least the maximum possible data error.

Abstract: A high-performance, pipelined CPU in which an improved method is used for saving registers in memory upon the occurrence of a procedure CALL or RETURN. The registers which need to be saved are defined by a bit-mask, and the number of bits is counted by a hardwired circuit, in each machine cycle, producing an output in the form of an offset from a stack pointer which represents the highest memory location needed to save the registers being used. Then a memory probe can be done to see if this location is writable. Thus, in one microinstruction cycle, the count is made and the memory probe can begin.

Abstract: A memory stack used for storing microinstruction addresses in a pipelined CPU is constructed as a last-in, first-out memory using a stack pointer which applies a read control to one location of the stack and applies a write control to the next higher location. An unconditional read and write is done every machine cycle, before a microinstruction could be decoded, then the data on the read bus, or data from the write bus, is used and the pointer is incremented or decremented if a stack Push or Pop is decoded. These correspond to a Call or Return microinstruction. Thus the delay in decoding the microinstruction does not prevent completion of the stack operation in one machine cycle.