Abstract: A processor supporting a translation lookaside buffer (TLB) modification instruction for updating a hardware-managed TLB is disclosed. A page table (PT) entry (PTE) corresponding to a virtual memory address is identified by a PT walking circuit walking the PT and a corresponding TLB entry is created. An execution circuit in the processor executes a TLB modification instruction to cause the TLB entry corresponding to the virtual memory address to be updated based on an update to the PT mapping information in the PTE corresponding to the virtual memory address. In one example, a portion of the PT mapping information in a PTE corresponding to a virtual memory address is stored in a TLB mapping information in a TLB entry corresponding to the virtual memory address in response to the TLB modification instruction being executed by the execution circuit without invalidating the TLB entry.

Abstract: Circuits, systems, and related methods to measure a performance characteristic(s) associated with a semiconductor die and adjust a clock signal based on the measured performance characteristic(s) are provided. The adjusted clock signal can be used to provide a clock signal to a functional circuit provided in the semiconductor die to assure proper operation of the functional circuit while operating with performance, voltage, temperature (PVT) delay variations. In this regard, a performance monitoring circuit is provided in the semiconductor die that includes the functional circuit. As a result, the performance monitoring circuit may be exposed to similar delay variations as the functional circuit. The performance monitoring circuit is configured to measure a performance characteristic(s) associated with the semiconductor die.

Abstract: Circuits, systems, and related methods to measure a performance characteristic(s) associated with a semiconductor die and adjust a clock signal based on the measured performance characteristic(s) are provided. The adjusted clock signal can be used to provide a clock signal to a functional circuit provided in the semiconductor die to assure proper operation of the functional circuit while operating with performance, voltage, temperature (PVT) delay variations. In this regard, a performance monitoring circuit is provided in the semiconductor die that includes the functional circuit. As a result, the performance monitoring circuit may be exposed to similar delay variations as the functional circuit. The performance monitoring circuit is configured to measure a performance characteristic(s) associated with the semiconductor die.