Abstract: The present invention provides a static random-access memory (SRAM) device that comprises a substrate having an insulator and a gate formed thereover, where the insulator electrically insulates the gate from the substrate, and a local conductive layer that is formed on the gate structure and that extends from the gate and onto the substrate. The local conductive layer is connectable to a conductive interconnect structure to connect the gate electrically to an other portion of the SRAM device. The SRAM device, in one embodiment, is part of a complementary metal oxide semiconductor (CMOS). However, it will be appreciated by those who are of ordinary skill the art that the present invention may be used in various types of metal oxide semiconductors and similar semiconductor devices in general.

Abstract: A semiconductor memory cell with parallel gates is disclosed. The direction of the gates is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved. Another embodiment of the invention features a connection between two conductive layers and a source/drain. The connection forms a node between one access transistor and one pull-down transistor.

Abstract: Integrated-circuit devices are provided with conductive paths or links which, by laser irradiation or electric current pulsing, can be severed or fused. In the interest of ease of fusing, preferred links have locally reduced thickness as achieved, e.g., by employing two steps of layer deposition and etching as follows: first, a layer of conductor material is deposited on a dielectric surface, and locally reduced in thickness by etching at one or several points selected for fusing, and, second, a further layer of conductor material is deposited, and then etched to produce a desired conductive path passing through such points.

Abstract: A semiconductor memory cell with parallel gates is disclosed. The direction of the gates is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved. Another embodiment of the invention features a connetion between two conductive layers and a source/drain. The connection forms a node between one access transistor and one pull-down transistor.

Abstract: Integrated-circuit devices are provided with conductive paths or links which, by laser irradiation or electric current pulsing, can be severed or fused. In the interest of ease of fusing, preferred links have locally reduced thickness as achieved, e.g., by employing two steps of layer deposition and etching as follows: first, a layer of conductor material is deposited on a dielectric surface, and locally reduced in thickness by etching at one or several points selected for fusing, and, second, a further layer of conductor material is deposited, and then etched to produce a desired conductive path passing through such points.

Abstract: An integrated circuit includes a conductive fusible link (14) that may be blown by laser energy. The dielectric material (15) covering the fuse is etched away to expose the fuse. A protective dielectric layer (30) is formed on the fuse to a controlled thickness less than that of the interlevel dielectric. The resulting structure prevents shorts between conductors that might otherwise occur due to debris from the fuse-blowing operation, and provides protection to the integrated circuit. In addition, the fuse blowing operation is more consistent from fuse to fuse.