Abstract: The data processing system, has at least one memory unit operatively connected to a memory bus, and further has an input/output (I/O) bus controller for interfacing at least one peripheral device to the data processing system. The data processing system comprises a first bus which provides a first transmission medium between the peripheral device and the memory bus. A second bus, provides a second transmission medium between a CPU and the memory bus. A logic element, interposed between the first and second bus, and the memory bus, interfaces the first and second bus to the memory bus in response to request signals from the first and second bus.

Abstract: An arbitration circuit comprises a plurality of enabling elements which determines when predetermined conditions exist to transmit a request signal. A first gate combines transmitted request signals to generate a combined request signal. A plurality of first latches, each first latch having a sequential priority order and operatively connected to a corresponding enabling element, and further connected to the output of the first gate, generates an enable and a disable signal. A plurality of second gates is included, each second gate is operatively connected to the first gate to receive the combined request signal, and each second gate operatively connected to the corresponding first latch to receive the enable signal.