Abstract: Disclosed is a method of chem-mech polishing an electronic component substrate. The method includes the following steps;obtaining a substrate having at least two features thereon or therein which have a different etch rate with respect to a particular etchant; andcontacting the substrate with a polishing pad while contacting the substrate with a slurry containing the etchant wherein the slurry includes abrasive particles, a transition metal chelated salt and a solvent for the salt.The chem-mech polishing causes the at least two features to be substantially coplanar. Also disclosed is the chem-mech polishing slurry.

Abstract: A method is disclosed for producing coplanar metal/insulator films on a substrate according to a chem-mech polishing technique. In one example, a substrate having a patterned insulating layer of dielectric material thereon, is coated with a layer of metal. The substrate is then placed in a parallel polisher and the metal is removed elsewhere except in the holes where it is left intact. This is made possible through the use of an improved selective slurry which removes the metal much faster than the dielectric material. The insulating layer may then be used as an automatic etch stop barrier.In a second example a substrate having a patterned metallic layer is coated with an insulating layer and then subjected to chem-mech polishing. The structure is coplanarized by the chem-mech removal of the insulating material from the high points of the structure at a faster rate than from the lower points. Optional etch stop layers also may be used.

Abstract: Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time.Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material.

Abstract: A method for forming a uniform layer of a material from a vapor phase onto the surface of an object at a high rate of deposition includes a heated reservoir for vaporizing the material to be deposited, a reactor containing the objects to be coated, and a vacuum device for flowing the gaseous material from the reservoir to the reactor. The mass flow rate of the gas from the reservoir is held constant by precisely controlling the pressure at the outlet of the reservoir and at the inlet of the reactor. In one embodiment the upstream pressure is controlled by a valve responsive to a pressure sensor at the reservoir outlet, and the downstream pressure is controlled by adjusting the vacuum in the reactor as measured by a pressure sensor at the reactor inlet.

Abstract: A system and method for forming a uniform layer of a material from a vapor phase onto the surface of an object at a high rate of deposition includes a heated reservoir for vaporizing the material to be deposited, a reactor containing the objects to be coated, and a vacuum device for flowing the gaseous material from the reservoir to the reactor. The mass flow rate of the gas from the reservoir is held constant by precisely controlling the pressure at the outlet of the reservoir and at the inlet of the reactor. In one embodiment the upstream pressure is controlled by a valve responsive to a pressure sensor at the reservoir outlet, and the downstream pressure is controlled by adjusting the vacuum in the reactor as measured by a pressure sensor at the reactor inlet.

Abstract: A wide precipitate-free-zone (PFZ) is formed at the surface of a semiconductor substrate and at the same time a high density of oxygen precipitate particles are produced beneath at the surface PFZ by a two step annealing process involving a first cycle of very rapidly heating the wafers to a first high temperature and a second cycle of very slowly heating the wafers to a second high temperature.