Patents by Inventor William J. Pelletier

William J. Pelletier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6928850
    Abstract: A method and apparatus for enabling z-axis offset of narrow metal ties straps in lead frames used for packaging integrated circuits to prevent bowing or distortion. Simultaneous offsetting of the tie strap and stress relief mechanisms are provided on both the front and back sides of the lead frame. Those mechanisms include indentations along the long or primary axis of each tie strap, coupled with depressions across the top surface both at the center of the lead frame and between the base of the off set and the chip attach locations to prevent bowing in small pad and no pad lead frames, in particular.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: August 16, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: William J. Pelletier, Wayne E. Mann
  • Publication number: 20040194529
    Abstract: A method and apparatus for enabling z-axis offset of narrow metal ties straps in lead frames used for packaging integrated circuits to prevent bowing or distortion. Simultaneous offsetting of the tie strap and stress relief mechanisms are provided on both the front and back sides of the lead frame. Those mechanisms include indentations along the long or primary axis of each tie strap, coupled with depressions across the top surface both at the center of the lead frame and between the base of the off set and the chip attach locations to prevent bowing in small pad and no pad lead frames, in particular.
    Type: Application
    Filed: April 19, 2004
    Publication date: October 7, 2004
    Inventors: William J. Pelletier, Wayne E. Mann
  • Patent number: 6755069
    Abstract: A method and apparatus for enabling z-axis offset of narrow metal ties straps in lead frames used for packaging integrated circuits to prevent bowing or distortion. Simultaneous offsetting of the tie strap and stress relief mechanisms are provided on both the front and back sides of the lead frame. Those mechanisms include indentations along the long or primary axis of each tie strap, coupled with depressions across the top surface both at the center of the lead frame and between the base of the off set and the chip attach locations to prevent bowing in small pad and no pad lead frames, in particular.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: June 29, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: William J. Pelletier, Wayne E. Mann