Abstract: A low power timekeeping system utilizes a state machine to first read seconds stored in a RAM and update seconds and then determine if the minutes requires updating. If the minutes do not require updating then the sequencer stops operation until the next update cycle. Similarly, the minutes, hours, days of the week, date of the month, month, and year are updated only as needed in each update cycle thereby lowering the power requirement needed by the timekeeping system.

Abstract: A real time clock plus user memory and extra memory integrated in a single circuit with access to the extra memory either by direct addressing or by providing the address as data to specified addresses in the user memory. Further, the user memory has two banks with the same addresses, and bank selection derives from a bit in another portion of the user memory.

Abstract: A real time clock plus user memory and extra memory integrated in a single circuit with access to the extra memory either by direct addressing or by providing the address as data to specified addresses in the user memory. Further, the user memory has two banks with the same addresses, and bank selection derives from a bit in another portion of the user memory.

Abstract: A low power timekeeping system utilizes a state machine to first read seconds stored in a RAM and update seconds and then determine if the minutes requires updating. If the minutes do not require updating then the sequencer stops operation until the next update cycle. Similarly, the minutes, hours, days of the week, date of the month, month, and year are updated only as needed in each update cycle thereby lowering the power requirement needed by the timekeeping system.

Abstract: Preferred embodiments have an external RAM controlled by logic on an internal RAM with overlapping address space. Read requests from addresses in the overlapping portion are directed to internal RAM only by controlling the output enable signal of external RAM; contrarily, writes to addresses in the overlapping portion proceed in both internal and external RAM simultaneously.

Abstract: A dynamic PLA timing circuit in a PLA ROM includes a PLA line and the address section only of another PLA line. The address section of the first PLA line is connected to the true address lines and the address section of the other PLA line is connected to the complementary address lines. Shorting bars connecting the two PLA lines are formed around each pair of true and complementary address lines such that a conductive path is formed through the address sections for any address into the ROM. The data section is connected to the gates of every data transistor. However, the drains of all but one of the data transistors are not connected to their associated data line. The data line that is connected to the associated data transistor forms the output terminal of the timing circuit.

Abstract: A low power timekeeping system utilizes a state machine to first read seconds stored in a RAM and update seconds and then determine if the minutes requires updating. If the minutes do not require updating then the sequencer stops operation until the next update cycle. Similarly, the minutes, hours, days of the week, date of the month, month, and year are updated only as needed in each update cycle thereby lowering the power requirement needed by the timekeeping system.

Abstract: An integrated circuit wherein remapping logic permits the output-driver characteristics of a given pin to changed in software, by changing the data stored in a nonvolatile control bit.

Abstract: Arbitration logic is provided to receive conflicts between a timekeeping system and a user system which share a common memory. The common memory is comprised of an array of dual memory cells, each of which has a timekeeping cell and a user cell and circuitry for transferring data from the timekeeping cell to the user cell or from the user cell to the timekeeping cell. User data is written into the user cells when it is available and immediately thereafter is transferred from the user cells to the timekeeping cells. Data from the timekeeping system is inhibited from being written into the timekeeping cells if, during the present update cycle of the timekeeping system, the user writes data into the common memory.

Abstract: An integrated circuit timekeeper, which uses a hybrid hardware/software architecture, wherein the least significant bits are updated in hardware and the more significant bits are updated in software. This hybrid architecture provides improved power efficiency, layout efficiency, and flexibility in reconfiguration.

Abstract: A low power timekeeping system utilizes a state machine to first read seconds stored in a RAM and update seconds and then determine if the minutes requires updating. If the minutes do not require updating then the sequencer stops operation until the next update cycle. Similarly, the minutes, hours, days of the week, date of the month, month, and year are updated only as needed in each update cycle thereby lowering the power requirement needed by the timekeeping system.

Abstract: A dynamic PLA timing circuit in a PLA ROM includes a first PLA line and the address section only of another PLA line. The address section of the first PLA line is connected to the true address lines and the address section of the other PLA line is connected to the complementary address lines. Shorting bars connecting the two PLA lines are formed around each pair of true and complementary address lines such that a conductive path is formed through the address sections for any address into the ROM. The data section is connected to the gates of every data transistor. However, the drains of all but one of the data transistors are not connected to their associated data line. The data line that is connected to the associated data transistor forms the output terminal of the timing circuit.

Abstract: A delay circuit that can be implemented in a monolithic integrated circuit includes a plurality of capacitor/laser-fusible link series pairs. Delay of a binary output signal of the circuit with respect to an input transition is directly proportional to the amount of capacitance connected into the circuit. Because the laser-fusible links can selectively be opened with a laser, the amount of capacitance connected into the circuit can incrementally be reduced; thus, the delay of the circuit is reducibly adjustable to a desired value. By including a plurality of conductive element/laser-fusible link series pairs in the delay circuit, the delay of the circuit is also increasingly adjustable.

Abstract: A sense circuit for sensing the transition of an input signal from a first logic state to a second logic state and making a corresponding logic transition on the output at a higher slew rate includes a first buffer stage having a complementary pair of transistors consisting of P-channel transistor (34) and N-channel transistor (32) having the drains thereof isolated by N-channel transistor (26). A precharge signal is connected to the gates of the transistors (34) and (32) to turn on transistor (32) and pull the drain thereof low. The drain of transistor (32) is connected to the gate of N-channel transistor (36). The P-channel transistor (26) is connected to an input signal and is operable to connect the drain of transistor (34) to the gate of transistor (36) when transistor (32) is turned off. This results in a node (38) being pulled from a high logic voltage to a low logic voltage when the input signal falls one V.sub.T below the source of transistor (26).