Abstract: A method and apparatus for a pulse width modulated (PWM) signal (30, 130) is provided. The input is a digital signal which is a modulated signal (24, 124). In the illustrated form, the modulated input signal is either a PDM signal or a PCM signal. In one embodiment of the present invention a PCM to PWM converter (16, 116) includes correction of duty ratio circuitry (48). The methodology used may include recursion on the values obtained after prediction, interpolation, and correction. The digital to analog conversion system (10) uses a PDM to PWM converter (20) which operates in an all digital domain and includes no analog circuitry.

Abstract: A method and apparatus for a pulse width modulated (PWM) signal (30, 130) is provided. The input is a digital signal which is a modulated signal (24, 124). In the illustrated form, the modulated input signal is either a PDM signal or a PCM signal. In one embodiment of the present invention a PCM to PWM converter (16, 116) includes correction of duty ratio circuitry (48). The methodology used may include recursion on the values obtained after prediction, interpolation, and correction. The digital to analog conversion system (10) uses a PDM to PWM converter (20) which operates in an all digital domain and includes no analog circuitry.

Abstract: A switching amplifier (15) includes a power stage (18) and a digital correction circuit (16). The digital correction circuit (16) is for correcting nonlinearity and power supply noise introduced into a digital signal during power stage amplification. The digital correction circuit (16) receives a digital pulse modulated input signal from a processor (14) and an amplified pulse modulated output signal from the power stage (18), and performs a discrete-time pulse edge correction on the digital pulse modulated input signal to provide a corrected digital pulse modulated signal. The corrected digital pulse modulated signal is used as an input for the power stage (18).

Abstract: A switching amplifier (15) includes a power stage (18) and a digital correction circuit (16). The digital correction circuit (16) is for correcting nonlinearity and power supply noise introduced into a digital signal during power stage amplification. The digital correction circuit (16) receives a digital pulse modulated input signal from a processor (14) and an amplified pulse modulated output signal from the power stage (18), and performs a discrete-time pulse edge correction on the digital pulse modulated input signal to provide a corrected digital pulse modulated signal. The corrected digital pulse modulated signal is used as an input for the power stage (18).

Abstract: A method and apparatus to produce a pulse width modulated (PWM) signal from pulse code modulated (PCM) data. In one embodiment, a crossing point of an analog signal with the ramp portion of a sawtooth waveform is approximated by first extrapolating, or projecting, a line between two adjacent sample points across other sample points to produce an estimate of the crossing point. A magnitude difference between a crossing point of the extrapolated line and a sample point magnitude on each side of the crossing point is determined. The magnitude difference, multiplied by an empirically determined constant, is added to the estimate. A PWM signal is then produced using the estimate for the crossing point.

Abstract: An electronic device (10) includes a signal processor (14) receiving an input signal requiring calibration, a data storage device (38) providing calibration data to the signal processor (14), a calibration controller (32) allowing the calibration data to be written to the data storage device (38) across at least an output terminal (22), and such that the signal processor (14) produces a calibrated output signal via an output driver (30) to the output terminal (22).

Abstract: In a communication unit a receiver (104) receives a modulated signal (118), and produces a received signal (120) having a parameter. The receiver (104) has a discontinuous receive mode of operation, wherein the receiver (104) is permitted to be turned on and off. Receiver circuitry (105) receives the received signal (120), and produces an output signal (124) having a parameter. A controller (110) adjusts a value of the parameter of the output signal (124), responsive to a value of the parameter of the received signal (120), during the times when the receiver (140) is turned on; and holds the value of the parameter of the output signal (124), responsive to the value of the parameter of the received signal (120), at the time when the receiver (104) is turned off. The present invention advantageously minimizes the turn on time for the receiver (104) operating in a discontinuous receive mode to save current drain.

Abstract: An interference dependent adaptive phase clock controller method and system includes synthesis of a signal processing clock signal (307). An interference signal (311 ) dependent on a phase of the signal processing clock signal is measured, and a phase correction signal (317) is provided dependent thereon. A magnitude of the interference signal is reduced by adjusting the phase of the signal processing clock signal (307) dependent on the phase correction signal (317).

Abstract: An apparatus and a method for minimizing the turn on time for a receiver operating in a discontinuous receive mode. In a communication unit the receiver receives a signal (118) having desirable data (word A) and undesirable data (word B). The receiver (104) has a discontinuous receive mode of operation wherein the receiver (104) is turned on when expecting the desirable data (word A) and turned off when expecting the undesirable data (word B). A duration of time that the receiver (104) has been turned off is determined. The receiver (104) is turned on at time prior to the arrival of the desirable data (word A) responsive to the duration of time that the receiver (104) has been turned off. The present invention advantageously minimizes the turn on time for the receiver (104) operating in a discontinuous receive mode to save current drain.