Abstract: A feedforward distortion cancellation circuit active control of both cancellation loops and a pilot signal and using least means squared circuits in both cancellation loops is disclosed. According to the invention, by using a pilot signal as the reference signal in a least means squared cancellation circuit, the required level of cancellation is reduced and thus it is easier to fabricate the circuit and the circuit is more stable.

Abstract: A low power digital receiver (10) is provided that contemporaneously selects the lowest possible sampling signal frequency (34) (from a plurality of available sampling signals), and received signal level (28) to properly digitize (32) and recover a desired signal. Digitization is performed after the first IF using broadband stages (28, 30, and 32) that are temporarily enabled (44) to rapidly digitize the first IF signal. This, together with the low sampling rate, minimizes the power consumption of the receiver (10) thereby permitting portable and mobile digital receiver embodiments.

Abstract: A digital radio receiver is described. The digital receiver of the present invention contemplates a digital radio receiver which operates on a received analog signal which has been converted to a digital form after preselection at the output of the antenna. The digital receiver of the present invention comprises a preselector, a high-speed analog-to-digital (A/D) converter, a digitally implemented intermediate-frequency (IF) selectivity section having an output signal at substantially baseband frequencies, and digital signal processor (DSP) circuit performing demodulation and audio filtering. The radio architecture of the present invention is programmably adaptable to virtually every known modulation scheme and is particularly suitable for implementation on integrated circuits.

Abstract: An improved apparatus and method for a sigma delta converter for bandpass signals is disclosed, suitable for use in mobile radio applications, between the front end and digital signal processing stages, that includes at least one bandpass filter, an n-level quantizer, an n-level digital-to-analog (D/A) converter, and a direct current (DC) feedback network. The sigma delta converter for bandpass signals may be configured in a second order or a fourth order embodiment and achieves analog-to-digital conversion of a signal having a non-zero frequency carrier or suppressed carrier with improved signal-to-noise ratio performance and with minimal quantization error. As a result, the sigma delta conversion occures earlier in a receiver chain and a dynamic range of about 95-98 dB is achieved.

Abstract: A low power digital receiver (10) is provided that contemporaneously selects the lowest possible sampling signal frequency (34) (from a plurality of available sampling signals), and received signal level (28) to properly digitize (32) and recover a desired signal. Digitization is performed after the first IF using broadband stages (28, 30, and 32) that are temporarily enabled (44) to rapidly digitize the first IF signal. This, together with the low sampling rate, minimizes the power consumption of the receiver (10) thereby permitting portable and mobile digital receiver embodiments.

Abstract: A phase-locked loop comprises a reference source that produces a signal at a fixed frequency that is applied to a phase detector. That signal is compared in the phase detector with a divided quotient signal that is proportional to the output of a voltage-controlled oscillator. Comparison of the phase difference between the two signals creates an output voltage that is taken to an adaptive filter. The adaptive filter is controlled by an external logic circuit that selects a narrow bandwidth when phase lock is detected and a wider bandwidth when the absence of phase lock is detected. The divisor of the divider in the loop is also changed in response to a signal based on the phase difference. The output of the adaptive filter is taken to a summer which adds a modulating signal to form a combined controlled voltage for the VCO.

Abstract: A circuit for automatic gain control of a feedback system in a time that is essentially constant regardless of the signal level includes a device for producing a signal that is representative of the output of the circuit. The signal is compared with a fixed reference to determine an error signal. The error signal is multiplied by its own time integral to obtain a control signal for a weighter that is cascaded with an amplifier to provide a controlled forward path. By this means, gain of the controlled forward path is controlled within a time that is substantially independent of signal strength.