Patents by Inventor William Jackson Bibb, JR.

William Jackson Bibb, JR. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10133584
    Abstract: The present disclosure describes several embodiments, e.g., a method, a baseboard management controller (BMC) system, a computer-readable non-transitory medium, for managing boot images for a computer system. These embodiments may include obtaining, by a BMC of the BMC system, a first boot image for the processor-based system, storing, by the BMC of the BMC system, the first boot image at a first location in a memory element of BMC system, and informing, by the BMC of the BMC system to a bus-to-memory bridge, first location information indicating a first location at which the first boot image is stored. The present disclosure also describes the bus-to-memory bridge which interfaces between a bus of the processor-based system and the memory element of the BMC system to allow one or more processors of the processor-based system to access the memory element of the BMC system to obtain boot image(s).
    Type: Grant
    Filed: March 4, 2017
    Date of Patent: November 20, 2018
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: William Jackson Bibb, Jr., Sunil Bhagia
  • Publication number: 20170177375
    Abstract: The present disclosure describes several embodiments, e.g., a method, a baseboard management controller (BMC) system, a computer-readable non-transitory medium, for managing boot images for a computer system. These embodiments may include obtaining, by a BMC of the BMC system, a first boot image for the processor-based system, storing, by the BMC of the BMC system, the first boot image at a first location in a memory element of BMC system, and informing, by the BMC of the BMC system to a bus-to-memory bridge, first location information indicating a first location at which the first boot image is stored. The present disclosure also describes the bus-to-memory bridge which interfaces between a bus of the processor-based system and the memory element of the BMC system to allow one or more processors of the processor-based system to access the memory element of the BMC system to obtain boot image(s).
    Type: Application
    Filed: March 4, 2017
    Publication date: June 22, 2017
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: William Jackson Bibb, Jr., Sunil Bhagia
  • Patent number: 9594571
    Abstract: The present disclosure describes several embodiments, e.g., a method, a baseboard management controller (BMC) system, a computer-readable non-transitory medium, for managing boot images for a computer system. These embodiments may include obtaining, by a BMC of the BMC system, a first boot image for the processor-based system, storing, by the BMC of the BMC system, the first boot image at a first location in a memory element of BMC system, and informing, by the BMC of the BMC system to a bus-to-memory bridge, first location information indicating a first location at which the first boot image is stored. The present disclosure also describes the bus-to-memory bridge which interfaces between a bus of the processor-based system and the memory element of the BMC system to allow one or more processors of the processor-based system to access the memory element of the BMC system to obtain boot image(s).
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: March 14, 2017
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: William Jackson Bibb, Jr., Sunil Bhagia
  • Publication number: 20150355911
    Abstract: The present disclosure describes several embodiments, e.g., a method, a baseboard management controller (BMC) system, a computer-readable non-transitory medium, for managing boot images for a computer system. These embodiments may include obtaining, by a BMC of the BMC system, a first boot image for the processor-based system, storing, by the BMC of the BMC system, the first boot image at a first location in a memory element of BMC system, and informing, by the BMC of the BMC system to a bus-to-memory bridge, first location information indicating a first location at which the first boot image is stored. The present disclosure also describes the bus-to-memory bridge which interfaces between a bus of the processor-based system and the memory element of the BMC system to allow one or more processors of the processor-based system to access the memory element of the BMC system to obtain boot image(s).
    Type: Application
    Filed: June 10, 2014
    Publication date: December 10, 2015
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: William Jackson Bibb, JR., Sunil Bhagia
  • Patent number: 8713295
    Abstract: A Cost-Reduced Enterprise Server (CRES) system includes a flexible resource-efficient server having a plurality of Processor Memory Boards (PMBs) coupled to an Input/Output Module (IOM). The IOM provides all networking and storage interfaces for the server. The IOM is implemented as a field-replaceable pluggable module, and thus all Input/Output (I/O) capabilities or resources of a CRES system may be upgraded via replacement of the IOM. Each PMB is dividable into a pair of Symmetric MultiProcessor (SMP) complexes, and each complex is coupled to a respective portion of the I/O resources provided by the IOM. Each portion of the IOM provides a pair of I/O daughter-module connectors compatible with standard I/O interfaces, such as Peripheral Component Interconnect (PCI)-X and PCI-Express. One or more CRES systems may be coupled to one or more Enterprise Server (ES) systems to form a multi-chassis server managed collectively as one or more provisioned servers.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: April 29, 2014
    Assignee: Oracle International Corporation
    Inventors: Daniel H. Bax, William Jackson Bibb, Jr., Russell M. Clapp, Tom Gourley, Geoffrey H. Hanson, Allen Hirashiki, Thomas Dean Lovett, Sharad Mehrotra, Shyam Mittur, Nakul Pratap Saraiya
  • Publication number: 20130117766
    Abstract: A Cost-Reduced Enterprise Server (CRES) system includes a flexible resource-efficient server having a plurality of Processor Memory Boards (PMBs) coupled to an Input/Output Module (IOM). The IOM provides all networking and storage interfaces for the server. The IOM is implemented as a field-replaceable pluggable module, and thus all Input/Output (I/O) capabilities or resources of a CRES system may be upgraded via replacement of the IOM. Each PMB is dividable into a pair of Symmetric MultiProcessor (SMP) complexes, and each complex is coupled to a respective portion of the I/O resources provided by the IOM. Each portion of the IOM provides a pair of I/O daughter-module connectors compatible with standard I/O interfaces, such as Peripheral Component Interconnect (PCI)-X and PCI-Express. One or more CRES systems may be coupled to one or more Enterprise Server (ES) systems to form a multi-chassis server managed collectively as one or more provisioned servers.
    Type: Application
    Filed: April 17, 2007
    Publication date: May 9, 2013
    Inventors: Daniel H. Bax, William Jackson Bibb, JR., Russell M. Clapp, Tom Gourley, Geoffrey H. Hanson, Allen Hirashiki, Thomas Dean Lovett, Sharad Mehrotra, Shyam Mittur, Nakul Pratap Saraiya