Abstract: Example embodiments of the systems and methods of CCM primary-side regulation disclosed herein subtract an estimate of the secondary IR drop from each output voltage sample. This allows a fixed sample instant to be set (with regard to the beginning of the off or flyback interval), and removes the need to hunt for or adjust to an optimum sample instant, or one with minimum IR drop error. The estimate of the IR drop may be adjusted on a cycle-by-cycle basis, based on the commanded primary peak current, knowing that the peak secondary current will be directly proportional by the turns ratio of the transformer. For improved accuracy, an adjustment may be made for the decay of secondary current during the delay to the sample instant, if the inductance value is known.

Abstract: A system includes a switching power supply that includes switch devices configured to provide a regulated output voltage based on an input voltage. A controller is configured to control the switch devices based on a power demand signal. A direct conduction avoidance circuit is configured to provide a direct conduction avoidance signal based on the regulated output voltage exceeding a direct conduction threshold voltage. The direct conduction avoidance signal is combined with a compensation signal to provide the power demand signal to the controller. An override circuit is configured to disable the direct conduction avoidance circuit based on the input voltage of the switching power supply being below an override threshold voltage.

Abstract: A power factor correction controller zero current detection circuit includes a differentiator circuit, a comparator, a first qualification timer circuit, an idle ringing detector circuit, a second qualification timer circuit, and a flip-flop. The comparator is coupled to the differentiator circuit. The first qualification timer circuit includes an input coupled to an output of the comparator. The idle ringing detector circuit includes a first input coupled to the output of the comparator, and a second input coupled to an output of the first qualification timer circuit. The second qualification timer circuit includes a first input coupled to the output of the first qualification timer circuit, and a second input coupled an output of the idle ringing detector circuit. The flip-flop includes a first input coupled to the output of the comparator, and a second input coupled to an output of the second qualification timer circuit.

Abstract: A system includes a switching power supply that includes switch devices configured to provide a regulated output voltage based on an input voltage. A controller is configured to control the switch devices based on a power demand signal. A direct conduction avoidance circuit is configured to provide a direct conduction avoidance signal based on the regulated output voltage exceeding a direct conduction threshold voltage. The direct conduction avoidance signal is combined with a compensation signal to provide the power demand signal to the controller. An override circuit is configured to disable the direct conduction avoidance circuit based on the input voltage of the switching power supply being below an override threshold voltage.

Abstract: This invention relates to a control circuit for a buck power factor correction (PFC) stage. Buck PFC stages are commonly used in low cost, high efficiency power converters. These buck PFC stages are typically controlled using a very slow control loop with a crossover frequency of the order of 10 to 20 Hz. However, such a slow response is unsuitable for applications requiring overvoltage protection. The present invention overcomes the problems with the known control circuits for buck PFC stages by implementing a two stage control circuit having a fast outer loop control circuit and a slow inner loop control circuit. The fast outer loop control circuit is in operation during low load conditions and the slow inner loop control circuit is only active under load.

Abstract: Example embodiments of the systems and methods of CCM primary-side regulation disclosed herein subtract an estimate of the secondary IR drop from each output voltage sample. This allows a fixed sample instant to be set (with regard to the beginning of the off or flyback interval), and removes the need to hunt for or adjust to an optimum sample instant, or one with minimum IR drop error. The estimate of the IR drop may be adjusted on a cycle-by-cycle basis, based on the commanded primary peak current, knowing that the peak secondary current will be directly proportional by the turns ratio of the transformer. For improved accuracy, an adjustment may be made for the decay of secondary current during the delay to the sample instant, if the inductance value is known.

Abstract: This invention relates to a control circuit for a buck power factor correction (PFC) stage. Buck PFC stages are commonly used in low cost, high efficiency power converters. These buck PFC stages are typically controlled using a very slow control loop with a crossover frequency of the order of 10 to 20 Hz. However, such a slow response is unsuitable for applications requiring overvoltage protection. The present invention overcomes the problems with the known control circuits for buck PFC stages by implementing a two stage control circuit having a fast outer loop control circuit and a slow inner loop control circuit. The fast outer loop control circuit is in operation during low load conditions and the slow inner loop control circuit is only active under load.

Abstract: An insulating footwear cover is provided for fitting over an article of footwear to shield same from outdoor elements. The cover includes an upper, and a wear-resistant sole portion extending beneath the bottom of the boot or shoe. The sole portion additionally overlaps a portion of the sides of the upper providing a wear-resistant patch over areas of the cover that are most susceptible to wear.