Patents by Inventor William Jared

William Jared has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11615805
    Abstract: A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: March 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Darin Edward Gerhart, Nicholas Edward Ortmeier, Cory Lappi, William Jared Walker
  • Patent number: 11416417
    Abstract: A method is provided that includes reading data in a storage medium, detecting, during the reading of the data in the storage medium, by a controller a change in an encryption/decryption scheme used to read and write the data in the storage medium, in response to detecting the change in encryption/decryption scheme in the data, causing, by the controller, a logical block address to return an indication of being written in zeros when a physical block address associated with the logical block address encrypted using an first encryption/decryption scheme, and causing, by the controller, a write channel to write zeroes using a second encryption/decryption scheme to the physical block address.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: August 16, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Darin Edward Gerhart, Cory Lappi, Daniel Robert Lipps, William Jared Walker
  • Patent number: 11288204
    Abstract: A method and arrangement are disclosed involving receiving a read-type command at a data storage arrangement, calculating a command span of the received read-type command and performing a look-up command, through use of a processor, for data located in each extent at a condensed logical block address state table for the read-type command, wherein the condensed logical block address state table describes a logical to physical table and at least one of transmitting data and displaying data related to the read-type command found in the condensed logical block address state table.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: March 29, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Darin Edward Gerhart, Cory Lappi, Nicholas Edward Ortmeier, William Jared Walker
  • Publication number: 20220076696
    Abstract: A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Darin Edward GERHART, Nicholas Edward ORTMEIER, Cory LAPPI, William Jared WALKER
  • Patent number: 11226811
    Abstract: The present disclosure generally relates to using a single firmware slot in a slower boot media while temporarily leveraging high speed media and dual boot designs to allow booting into a cached copy of firmware to guarantee power safety while writing the single firmware slot on the slower boot media. The device boots up with original firmware stored in a first non-volatile memory device when powered on. The device then checks a second non-volatile memory device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware. The device then writes the new firmware to the firmware slot of the first non-volatile memory device. If the device experiences a power cycle while writing the new firmware, the device can reboot with a cached copy of the new firmware.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: January 18, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Cory Lappi, William Jared Walker, Xin Chen
  • Patent number: 11195548
    Abstract: A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: December 7, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Darin Edward Gerhart, Nicholas Edward Ortmeier, Cory Lappi, William Jared Walker
  • Publication number: 20210232385
    Abstract: The present disclosure generally relates to using a single firmware slot in a slower boot media while temporarily leveraging high speed media and dual boot designs to allow booting into a cached copy of firmware to guarantee power safety while writing the single firmware slot on the slower boot media. The device boots up with original firmware stored in a first non-volatile memory device when powered on. The device then checks a second non-volatile memory device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware. The device then writes the new firmware to the firmware slot of the first non-volatile memory device. If the device experiences a power cycle while writing the new firmware, the device can reboot with a cached copy of the new firmware.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Cory LAPPI, William Jared WALKER, Xin CHEN
  • Patent number: 10990380
    Abstract: The present disclosure generally relates to using a single firmware slot in a slower boot media while temporarily leveraging high speed media and dual boot designs to allow booting into a cached copy of firmware to guarantee power safety while writing the single firmware slot on the slower boot media. The device boots up with original firmware stored in a first non-volatile memory device when powered on. The device then checks a second non-volatile memory device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware. The device then writes the new firmware to the firmware slot of the first non-volatile memory device. If the device experiences a power cycle while writing the new firmware, the device can reboot with a cached copy of the new firmware.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: April 27, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Cory Lappi, William Jared Walker, Xin Chen
  • Patent number: 10922070
    Abstract: A method for performing a download operation is described comprising detecting an updated firmware for installation, transmitting at least one slice of the updated firmware from an updated firmware location to a second firmware location, determining if a synchronization has completed with the at least one slice of the updated firmware and determining if additional slices are to be synchronized when the synchronization has completed with the at least one slice of the updated firmware.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: February 16, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Cory Lappi, William Jared Walker, Xin Chen
  • Patent number: 10922242
    Abstract: The present disclosure describes logical to physical tables that are configured to provide multiple sector support and provide for help in processing of data when a sector is mapped or unmapped. In the cases where sectors are unmapped, the present disclosure provides mechanisms to concurrently support multiple unique unmapped data patterns depending upon the specific type of unmapped sector.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: February 16, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Cory Lappi, William Jared Walker, Darin Edward Gerhart
  • Patent number: 10831657
    Abstract: The present disclosure generally relates to a storage device sensing critical failure or PLI events and writing the debug data to a memory device so that when boot-up occurs, at least some debug data is available. A dedicated hardware unit detects when one or more critical failure conditions occur by monitoring the one or more critical failure conditions. The critical failure conditions being detected or sensed triggers the dedicated hardware unit to automatically write debug data stored in a volatile memory device to a non-volatile memory device. The debug data stored in the non-volatile memory device provides a critical failure or PLI trace to determine what occurred leading up to and during a critical failure event. By writing the debug data to the non-volatile memory device, the critical failure trace may be accessed and analyzed after the device powers down or fails.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 10, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, Inc.
    Inventors: Cory Lappi, William Jared Walker, Xin Chen
  • Publication number: 20200349086
    Abstract: A method and arrangement are disclosed involving receiving a read-type command at a data storage arrangement, calculating a command span of the received read-type command and performing a look-up command, through use of a processor, for data located in each extent at a condensed logical block address state table for the read-type command, wherein the condensed logical block address state table describes a logical to physical table and at least one of transmitting data and displaying data related to the read-type command found in the condensed logical block address state table.
    Type: Application
    Filed: July 17, 2020
    Publication date: November 5, 2020
    Inventors: Darin Edward GERHART, Cory LAPPI, Nicholas Edward ORTMEIER, William Jared WALKER
  • Publication number: 20200342898
    Abstract: A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 29, 2020
    Inventors: Darin Edward GERHART, Nicholas Edward ORTMEIER, Cory LAPPI, William Jared WALKER
  • Publication number: 20200310989
    Abstract: A method is provided that includes reading data in a storage medium, detecting, during the reading of the data in the storage medium, by a controller a change in an encryption/decryption scheme used to read and write the data in the storage medium, in response to detecting the change in encryption/decryption scheme in the data, causing, by the controller, a logical block address to return an indication of being written in zeros when a physical block address associated with the logical block address encrypted using an first encryption/decryption scheme, and causing, by the controller, a write channel to write zeroes using a second encryption/decryption scheme to the physical block address.
    Type: Application
    Filed: May 18, 2020
    Publication date: October 1, 2020
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Darin Edward Gerhart, Cory Lappi, Daniel Robert Lipps, William Jared Walker
  • Patent number: 10761834
    Abstract: The present disclosure generally relates to using a dual-boot process where existing storage device firmware remains intact while the new firmware is downloaded to a non-volatile location on a fast non-volatile memory drive.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: September 1, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Cory Lappi, William Jared Walker, Xin Chen
  • Patent number: 10761937
    Abstract: The present disclosure generally relates to recovering storage devices in-field without the need to return the storage device to the factory. The storage device tracks detailed failure information. After receiving a signal or sequence of commands from a host device to prepare the storage device for a recovery download, the storage device determines whether to enter an adaptive field recovery state or a host-selected recovery state. If the storage device enters the adaptive field recovery state, the storage device determines which error state the device is in based on the detailed failure information, and selects an appropriate recovery level. After selecting the appropriate recovery level while in the adaptive field recovery state or after entering the host-selected recovery state, the storage device receives and downloads a recovery download package. The recovery download package comprises one or more recovery actions necessary to repair the error state.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: September 1, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Cory Lappi, William Jared Walker, Xin Chen
  • Patent number: 10726865
    Abstract: A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Darin Edward Gerhart, Nicholas Edward Ortmeier, Cory Lappi, William Jared Walker
  • Patent number: 10725931
    Abstract: A method and arrangement are disclosed involving receiving a read-type command at a data storage arrangement, calculating a command span of the received read-type command and performing a look-up command, through use of a processor, for data located in each extent at a condensed logical block address state table for the read-type command, wherein the condensed logical block address state table describes a logical to physical table and at least one of transmitting data and displaying data related to the read-type command found in the condensed logical block address state table.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: July 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Darin Edward Gerhart, Cory Lappi, Nicholas Edward Ortmeier, William Jared Walker
  • Patent number: 10698840
    Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of all zeroes is returned in response to an indication of another encryption/decryption method.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: June 30, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Darin Edward Gerhart, Cory Lappi, Daniel Robert Lipps, William Jared Walker
  • Patent number: 10649909
    Abstract: A device having a controller configured to execute a range crawler algorithm residing in firmware or hardware and a data table containing one or more range entries (RE's), where each of the RE's is part of a logical block address (LBA) span associated with a command instruction, and where each LBA span has one or more LBA ranges, and where each LBA range is made of one or more sequential LBA's. The device also includes a collision bitmap configured to store data associated with RE collisions between one or more LBA's and a command dispatcher configured to release selected LBA ranges that are not associated with a RE collision. The range crawler algorithm is configured to search the data table to detect collisions between the RE's.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: May 12, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Cory Lappi, Darin Edward Gerhart, Nicholas Edward Ortmeier, William Jared Walker