Patents by Inventor William Jiang
William Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10775625Abstract: The present disclosure provides systems and methods to enable significant improvements in display systems utilizing projectors and a retro-reflective (RR) screen through use of transparent or semi-transparent RR material. An aspect of the present disclosure provides methods for optimization of optical properties of the RR material to achieve desired optical transparency parameters. Another aspect of the present disclosure provides methods for specific use cases for flexible, transparent and semi-transparent RR display systems.Type: GrantFiled: February 1, 2019Date of Patent: September 15, 2020Assignee: MirraViz, Inc.Inventors: Michael W. Wang, David Jiang, William Jiang
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Publication number: 20190339524Abstract: The present disclosure provides systems and methods to enable significant improvements in display systems utilizing projectors and a retro-reflective (RR) screen through use of transparent or semi-transparent RR material. An aspect of the present disclosure provides methods for optimization of optical properties of the RR material to achieve desired optical transparency parameters. Another aspect of the present disclosure provides methods for specific use cases for flexible, transparent and semi-transparent RR display systems.Type: ApplicationFiled: February 1, 2019Publication date: November 7, 2019Inventors: Michael W. Wang, David Jiang, William Jiang
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Patent number: 9146616Abstract: A remote control device comprises a housing cover configured to mate with a touch-enabled surface configured to receive input gestures, and a battery holder disposed between the housing cover and the touch-enabled surface. A first plurality of magnets is disposed in the housing cover. A second plurality of magnets is disposed in the battery holder. The first plurality of magnets in the housing cover is attracted to the second plurality of magnets in a first position of the housing cover relative to the battery holder. The first plurality of magnets in the housing cover is repelled from the second plurality of magnets in a second position of the housing cover relative to the battery holder. The first position and the second position share a rotational axis normal to the touch-enabled surface.Type: GrantFiled: November 8, 2012Date of Patent: September 29, 2015Assignee: Fanhattan Inc.Inventors: Gilles Serge BianRosa, Olivier Chalouhi, Gregory Smelzer, William Jiang, Christopher Vinckier
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Publication number: 20140082497Abstract: A system and method for providing a user interface for live media content is described. A top portion of the user interface is populated with media content categories. A selection of a media content category from the media content categories is received. A bottom portion of the user interface is populated with at least one panel relating to the selection of media content category. A timeline comprising a progress indicator corresponding to a progress of a live media content associated with the at least one panel is generated in the user interface.Type: ApplicationFiled: September 17, 2013Publication date: March 20, 2014Applicant: Fanhattan LLCInventors: Olivier Chalouhi, Gilles Serge BianRosa, Nicolas Paton, William Jiang
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Patent number: 8434047Abstract: A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.Type: GrantFiled: January 25, 2011Date of Patent: April 30, 2013Assignee: Synopsys, Inc.Inventors: Yunjian (William) Jiang, Arvind Srinivasan, Joy Banerjee, Yinghua Li, Partha Das, Samit Chaudhuri
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Patent number: 7958476Abstract: A power optimization method of deriving gated circuitry in an integrated circuit (IC) is provided. A design description of the IC is received and analyzed. A state machine is identified based on the analysis. One or more candidate blocks are determined to be capable of being disabled. At least one of the candidate blocks is selected based on one or more states of the state machine. A gating circuit is inserted for gating the selected candidate block(s). In another embodiment of power optimization, one or more state machines are identified and a synthesized netlist is generated. One or more candidate blocks in the synthesized netlist are determined to be capable of being disabled. At least one of the candidate blocks is selected based on one or more states in the state machine, and a gating circuit is inserted for gating the selected candidate block(s).Type: GrantFiled: July 9, 2008Date of Patent: June 7, 2011Assignee: Magma Design Automation, Inc.Inventors: Yunjian (William) Jiang, Arvind Srinivasan, Samit Chaudhuri
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Patent number: 7930673Abstract: A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.Type: GrantFiled: May 28, 2008Date of Patent: April 19, 2011Assignee: Magma Design Automation, Inc.Inventors: Yunjian (William) Jiang, Arvind Srinivasan, Joy Banerjee, Yinghua Li, Partha Das, Samit Chaudhuri
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Patent number: 7882461Abstract: A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.Type: GrantFiled: May 28, 2008Date of Patent: February 1, 2011Assignee: Magma Design Automation, Inc.Inventors: Yunjian (William) Jiang, Arvind Srinivasan, Joy Banerjee, Yinghua Li, Partha Das, Samit Chaudhuri
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Publication number: 20090002056Abstract: Embodiments of the invention provide a circuit to implement an on-chip resistor with desired temperature coefficient behavior. In some embodiments, a circuit may comprise an amplifier, with a reference controlled by ratioed amounts of one or more positive temperature coefficient (TC+) and/or negative temperature coefficient (TC?) circuits, coupled to a controllable resistor device to control it as temperature changes to track the desired temperature coefficient behavior.Type: ApplicationFiled: June 30, 2007Publication date: January 1, 2009Inventors: James T. Doyle, William Jiang
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Publication number: 20080301594Abstract: A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.Type: ApplicationFiled: May 28, 2008Publication date: December 4, 2008Applicant: Magma Design Automation, Inc.Inventors: Yunjian (William) Jiang, Arvind Srinivasan, Joy Banerjee, Yinghua Li, Partha Das, Samit Chaudhuri
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Publication number: 20080301593Abstract: A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.Type: ApplicationFiled: May 28, 2008Publication date: December 4, 2008Applicant: Magma Design Automation, Inc.Inventors: Yunjian (William) Jiang, Arvind Srinivasan, Joy Banerjee, Yinghua Li, Partha Das, Samit Chaudhuri
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Publication number: 20080159292Abstract: A method of routing a data packet in a communication system includes receiving a data packet at a first communication party operating in accordance with a first protocol. The method also includes adding a header to the data packet to produce modified data packet, the header including an identifier identifying the first protocol, first protocol information, an identifier identifying a second protocol, and second protocol information, and then sending the modified data packet to a second communication party operating in accordance with the second protocol through a first connection.Type: ApplicationFiled: April 30, 2007Publication date: July 3, 2008Inventors: William Jiang, Ricky Li, Gene Liu, Tony Ouyang, Richard Sun
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Publication number: 20030172282Abstract: An improved methodology and implementing system are provided in which a number of different user ID and password combinations are assigned to the user. Each combination is associated with a different service which may be requested by the user. When a user ID and password combination is uploaded from a terminal to a server, the server system compares the combination with a stored memory of associations to determine which of several possible services is being requested by the user. In one example, a server will respond to a first combination to enable normal processing of a money transaction at an ATM terminal, but will respond to a second combination to effect notification of authorities that a distress situation such as a robbery is occurring at the terminal.Type: ApplicationFiled: March 7, 2002Publication date: September 11, 2003Applicant: International Business Machines CorporationInventor: William Jiang