Patents by Inventor William John Goetzinger

William John Goetzinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Weighted fair queue serving plural output ports
    Publication number: 20030081549
    Abstract: A data communication apparatus includes a plurality of output ports and a scheduler for assigning priorities for outbound data frames. The scheduler includes one or more scheduling queues. Each scheduling queue indicates an order in which data flows are to be serviced. At least one scheduling queue has a respective plurality of output ports assigned to the scheduling queue. That is, the scheduling queue is shared by two or more output ports.
    Type: Application
    Filed: November 1, 2001
    Publication date: May 1, 2003
    Applicant: International Business Machines Corporation
    Inventors: William John Goetzinger, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
  • Empty indicators for weighted fair queues
    Publication number: 20030081542
    Abstract: A scheduler for a network processor includes one or more scheduling queues. Each scheduling queue defines a respective sequence in which flows are to be serviced. A respective empty indicator is associated with each scheduling queue to indicate whether the respective scheduling queue is empty. By referring to the empty indicators, it is possible to avoid wasting operating cycles of the scheduler on searching scheduling queues that are empty.
    Type: Application
    Filed: November 1, 2001
    Publication date: May 1, 2003
    Applicant: International Business Machines Corporation
    Inventors: William John Goetzinger, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard, Daniel James Sucher
  • High speed network processor
    Publication number: 20020122386
    Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.
    Type: Application
    Filed: April 19, 2001
    Publication date: September 5, 2002
    Applicant: International Business Machines Corporation
    Inventors: Jean Louis Calvignac, William John Goetzinger, Glen Howard Handlogten, Marco C. Heddes, Joseph Franklin Logan, James Francis Mikos, David Alan Norgaard, Fabrice Jean Verplanken