Abstract: A high-speed correlator includes a serial-to-parallel convertor, and a pattern detector. The serial-to-parallel converter converts from ECL to TTL logic. The pattern detector includes a fast latch data pipe, high-speed RAMs and a fast adder. The data pipe applies the received data to the high-speed RAMs as address bits. Depending upon position and errors in the synchronization pattern various locations in the RAM are addressed. By preloading the RAM with appropriate data for a given synchronization pattern, position and error information is read from the addressed location and applied to correlate the data and determine the error content.