Abstract: A method, apparatus, system, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.

Abstract: A method, apparatus, system, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.

Abstract: A method, apparatus, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.

Abstract: An integrated circuit chip having at least one source pin and a plurality of sink pins. A wire segment connects the source pin to at least one of the sink pins and includes at least two segments where one of the segments is larger than the other where electromigration is likely to occur.

Abstract: A computerized tool or method that calculates the capacitance and resistance of each global wire on the chip, one wire at a time. The invention steps along a track containing a wire segment, grid point by grid point, calculating the resistance and capacitance at that point. At each grid point it searches the neighboring tracks within the surrounding cube for adjacent elements that could cause capacitive effects or affect the resistance of the wire. The method delivers capacitance and resistance values for each process condition for a grid unit length of wire, given the wire type and 3 dimensional environment of the wire segment. The capacitance and resistance at a grid point along the wire are generally determined by one table lookup for wire types based on the surrounding environment. These values are added along wire segments to deliver accurate 3 dimensional capacitances and resistances.

Abstract: A wiring design tool which detects minimum area vias and replaces them with redundant vias pairs. The invention uses the definitions for single vias and tracks in a grid coordinate system and a file describing the design wires and their interconnections to select the most favorable direction for the placement. The invention accomplishes this by examining the directions one track away from each single via at various levels and according to the methodology of this invention, detects a possible situs for a redundant via pair, preferably where a segment of wire on the same net already exists. If no design rule violation occurs the system replaces the single via with a redundant via pair.

Abstract: A method for wiring IC chips such that electromigration criteria are met while minimizing the effect on overall chip wireability. A technique to optimize the width of automatically routed wire segments so that these widths are adequate to support the electromigration current on that net as a function of the capacitive loading of the net itself.