Patents by Inventor William John McFarland

William John McFarland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-channel binding in data transmission
    Patent number: 7620028
    Abstract: A system and method are described for binding together a plurality of wireless data communications channels, whereby an aggregate throughput improvement is realized. A master channel amongst the channels to be bound is compatible with existing standards-based wireless data communications equipment. The master channel serves to perform MAC association and flow control. Aggregate throughput is improved by sending and receiving either multiple sets of separately encoded packets, commonly encoded packets or redundantly encoded packets.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: November 17, 2009
    Assignee: Atheros Communications, Inc.
    Inventors: Paul Husted, William John McFarland, Jeffrey M. Gilbert
  • System for providing electrostatic discharge protection for high-speed integrated circuits
    Patent number: 6597227
    Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: July 22, 2003
    Assignee: Atheros Communications, Inc.
    Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland
  • System for providing electrostatic discharge protection for high-speed integrated circuits
    Patent number: 6593794
    Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: July 15, 2003
    Assignee: Atheros Communications
    Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland
  • System for providing electrostatic discharge protection for high-speed integrated circuits
    Patent number: 6509779
    Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: January 21, 2003
    Assignee: Atheros Communications, Inc.
    Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland
  • System for providing electrostatic discharge protection for high-speed integrated circuits
    Publication number: 20020125931
    Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.
    Type: Application
    Filed: February 7, 2002
    Publication date: September 12, 2002
    Applicant: ATHEROS COMMUNICATIONS, INC.
    Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland
  • System for providing electrostatic discharge protection for high-speed integrated circuits
    Publication number: 20020121924
    Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.
    Type: Application
    Filed: February 7, 2002
    Publication date: September 5, 2002
    Applicant: ATHEROS COMMUNICATIONS, INC.
    Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland