Abstract: A process for forming a bipolar junction transistor (BJT) in a semiconductor substrate and a BJT formed according to the process. A buried isolation region is formed underlying BJT structures to isolate the BJT structures from the p-type semi-conductor substrate. To reduce capacitance between a BJT subcollector and the buried isolation region, prior to implanting the subcollector spaced-apart structures are formed on a surface of the substrate. The subcollector is formed by implanting ions through the spaced-apart structures and through a region intermediate the spaced-apart structures. The formed BJT subcollector therefore comprises a body portion and end portions extending therefrom, with the end portions disposed at a shallower depth than the body portion, since the ions implanting the end portions must pass through the spaced-apart structures. The shallower depth of the end portions reduces the capacitance.

Abstract: The present invention provides a method of manufacturing a bipolar transistor. The method may comprise forming a collector in a semiconductor wafer substrate, forming a base in the collector, implanting an oxide region within said collector and over the base, and forming an emitter over the substrate such that the oxide region is located between the emitter and the base.

Abstract: An SRAM cell within a semiconductor device includes p-channel transistors with increased threshold voltages to suppress standby leakage current in the SRAM cell. Existing processing operations already being used to form the semiconductor device, are used to produce the SRAM p-channel devices to have higher threshold voltages than logic p-channel devices also included within the semiconductor device. The processing operations used to form thicker gate oxides for transistors in the I/O portion of the same semiconductor device, may be used to form increased gate oxide thicknesses within the SRAM p-channel transistors. The SRAM p-channel transistors may include a gate oxide that is thicker than the gate oxides of the SRAM n-channel transistors and the logic p-channel transistors. In another embodiment, the gates of the SRAM p-channel transistors may be counterdoped with n-type impurities to produce an effectively greater gate oxide thickness due to poly depletion.

Abstract: The present invention provides a method of manufacturing a bipolar transistor. The method may comprise forming a collector in a semiconductor wafer substrate, forming a base in the collector, implanting an oxide region withing said collector and over the base, and forming an emitter over the substrate such that the oxide region is located between the emitter and the base.

Abstract: A bipolar fabrication process, illustratively suited for integration into a conventional CMOS process to thereby form a BiCMOS integrated circuits is disclosed. The collector and base are formed through multiple implants and a single masking step to thereby provide a continuous low resistance collector region.