Abstract: A DC offset compensation circuit (34) for compensating for a DC offset voltage of a signal amplifier (24) includes a first sample and hold circuit (40) having an input receiving an amplifier output signal (VOUT2) and an output supplying the sampled and held output signal (VOUT2) to a non-inverting input of a comparator 42. A first digital-to-analog (D/A) circuit (46) is responsive to a number of digital input signals to produce an analog DC target signal at an output (VD) thereof. The analog DC target signal is provided to an input of a second sample and hold circuit (50) having an output supplying the sampled and held analog DC target signal to an inverting input of the comparator 42. The output of the comparator 42 is provided to an offset cancellation control circuit (56) including a state machine (66) and a counter circuit (68) operable to modify a count value (OFFDAC) thereof depending upon statuses of a number of input control signals (CLK1, CLK2, STRT, STP) and the comparator output signal (CO).