Abstract: Systems and methods for product imaging and provisioning include a mobile application (app) installed on an imaging device, where the mobile app activates the imaging device to generate an image of a product tag associated with an unavailable product at a first location. The mobile app determines, based on the image, a product indicator associated with the unavailable product. A provisioning app, executing on a remote device, receives the product indicator associated with the unavailable product. The provisioning app also receives a user indicator associated with a first user and executes one or more product provisioning rules that determine, based on a product availability database and the user indicator, an availability result. The availability result indicates whether the unavailable product will be available to the first user. The provisioning app is further operable to send the availability result to the imaging device for presentation by the imaging device.

Abstract: An imaging system captures one or more images at a time when a subject is comfortably wearing a pair of glasses with dummy lenses. The subject's face is illuminated by energy sources (e.g. visible light sources), and specular reflections (“glints”) from the dummy lenses used to measure the locations the dummy lens(es). This provides information about how the comfortable positions for glasses on the subject's face, which can be used to design and fabricate personalized glasses.

Abstract: An imaging system captures one or more images at a time when a subject is comfortably wearing a pair of glasses with dummy lenses. The subject's face is illuminated by energy sources (e.g. visible light sources), and specular reflections (“glints”) from the dummy lenses used to measure the locations the dummy lens(es). This provides information about how the comfortable positions for glasses on the subject's face, which can be used to design and fabricate personalized glasses.

Abstract: A method of extracting unclassified data from a collection of data including both classified data and unclassified data, includes: providing a plain text format file including a plurality of attributes; using the attributes to identify unclassified data within a collection of data that includes a combination of unclassified and classified data; and extracting the identified unclassified data from the collection of data. An apparatus that implements the method is also provided.

Abstract: A method of extracting unclassified data from a collection of data including both classified data and unclassified data, includes: providing a plain text format file including a plurality of attributes; using the attributes to identify unclassified data within a collection of data that includes a combination of unclassified and classified data; and extracting the identified unclassified data from the collection of data. An apparatus that implements the method is also provided.

Abstract: A processor including a large register file utilizes a dirty bit storage coupled to the register file and a dirty bit logic that controls resetting of the dirty bit storage. The dirty bit logic determines whether a register or group of registers in the register file has been written since the process was loaded or the context was last restored and, if written generates a value in the dirty bit storage that designates the written condition of the register or group of registers. When the context is next saved, the dirty bit logic saves a particular register or group of registers when the dirty bit storage indicates that a register or group of registers was written. If the register or group of registers was not written, the context is switched without saving the register or group of registers. The dirty bit storage is initialized when a process is loaded or the context changes.

Abstract: A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.

Abstract: A system and method for establishing communications channels between and among peers in a peer-to-peer networking environment. Pipes may be used as communication channels for sending and receiving messages and other data between services or applications over input and output endpoints. Pipes may be asynchronous, unidirectional, stateless and unreliable. Bidirectional pipes may also be supported. Pipes may have ends that may be moved around and bound to different peers at different times. Point-to-point and propagate pipes may be supported. Pipes may connect peers that have a direct physical link and peers that do not have a direct link. Peers may communicate through pipes without knowing on which peer a pipe endpoint is bound. A message is sent to all peer endpoints currently connected (listening) to the pipe. The set of connected endpoints may be obtained from a pipe service using a pipe binding protocol.

Abstract: A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.

Abstract: A Very Long Instruction Word (VLIW) processor having a plurality of functional units includes a multi-ported register file that is divided into a plurality of separate register file segments, each of the register file segments being associated to one of the plurality of functional units. The register file segments are partitioned into local registers and global registers. The global registers are read and written by all functional units. The local registers are read and written only by a functional unit associated with a particular register file segment. The local registers and global registers are addressed using register addresses in an address space that is separately defined for a register file segment/functional unit pair. The global registers are addressed within a selected global register range using the same register addresses for the plurality of register file segment/functional unit pairs.

Abstract: The present invention relates to antibodies including human antibodies and antigen-binding portions thereof that bind to P-cadherin, and that function to inhibit P-cadherin. The invention also relates to heavy and light chain immunoglobulins derived from human P-cadherin antibodies and nucleic acid molecules encoding such immunoglobulins. The present invention also relates to methods of making human P-cadherin antibodies, compositions comprising these antibodies and methods of using the antibodies and compositions. The invention also relates to transgenic animals or plants comprising nucleic acid molecules of the present invention.

Abstract: A processor including a large register file utilizes a dirty bit storage coupled to the register file and a dirty bit logic that controls resetting of the dirty bit storage. The dirty bit logic determines whether a register or group of registers in the register file has been written since the process was loaded or the context was last restored and, if written generates a value in the dirty bit storage that designates the written condition of the register or group of registers. When the context is next saved, the dirty bit logic saves a particular register or group of registers when the dirty bit storage indicates that a register or group of registers was written. If the register or group of registers was not written, the context is switched without saving the register or group of registers. The dirty bit storage is initialized when a process is loaded or the context changes.

Abstract: A processor executes an instruction set including instructions in which a register specifier is implicitly derived, based on another register specifier. One technique for implicitly deriving a register specifier is to add or subtract one from a specifically-defined register specifier. Implicit derivation of a register specifier is selectively implemented for some opcodes. A decoder decodes instructions that use implicitly-derived register specifiers and reads the explicitly-defined register. The decoder generates pointers both to the explicitly-defined register and to the implicitly-derived register. In other embodiments, a pointer to registers within a register file includes an additional bit indicating that a register read is accompanied by a read of an implicitly-derived register.

Abstract: A Very Long Instruction Word (VLIW) processor having a plurality of functional units includes a multi-ported register file that is divided into a plurality of separate register file segments, each of the register file segments being associated to one of the plurality of functional units. The register file segments are partitioned into local registers and global registers. The global registers are read and written by all functional units. The local registers are read and written only by a functional unit associated with a particular register file segment. The local registers and global registers are addressed using register addresses in an address space that is separately defined for a register file segment/functional unit pair. The global registers are addressed within a selected global register range using the same register addresses for the plurality of register file segment/functional unit pairs.

Abstract: A processor including a large register file utilizes a dirty bit storage coupled to the register file and a dirty bit logic that controls resetting of the dirty bit storage. The dirty bit logic determines whether a register or group of registers in the register file has been written since the process was loaded or the context was last restored and, if written generates a value in the dirty bit storage that designates the written condition of the register or group of registers. When the context is next saved, the dirty bit logic saves a particular register or group of registers when the dirty bit storage indicates that a register or group of registers was written. If the register or group of registers was not written, the context is switched without saving the register or group of registers. The dirty bit storage is initialized when a process is loaded or the context changes.

Abstract: A processor has an improved architecture for multiple-thread operation on the basis of a highly parallel structure including multiple independent parallel execution paths for executing in parallel across threads and a multiple-instruction parallel pathway within a thread. The multiple independent parallel execution paths include functional units that execute an instruction set including special data-handling instructions that are advantageous in a multiple-thread environment.

Abstract: A processor has an improved architecture for multiple-thread operation on the basis of a highly parallel structure including multiple independent parallel execution paths for executing in parallel across threads and a multiple-instruction parallel pathway within a thread. The multiple independent parallel execution paths include functional units that execute an instruction set including special data-handling instructions that are advantageous in a multiple-thread environment.

Abstract: A Very Long Instruction Word (VLIW) processor has a clustered architecture including a plurality of independent functional units and a multi-ported register file that is divided into a plurality of separate register file segments, the register file segments being individually associated with the plurality of independent functional units. The functional units access the respective associated register file segments using read operations that are local to the functional unit/ register file segment pairs. In contrast, the functional units access the register file segments using write operations that are broadcast to a plurality of register file segments. Independence between clusters is attained since the separate clustered functional unit/ register file segment pairs have local (internal) bypassing that allows internal computations to proceed, but have only limited bypassing between different functional unit/ register file segment pair clusters.

Abstract: A multi-ported register file is typically metal limited to the area consumed by the circuit proportional with the square of the number of ports. A processor having a register file structure divided into a plurality of separate and independent register files forms a layout structure with an improved layout efficiency. The read ports of the total register file structure are allocated among the separate and individual register files. Each of the separate and individual register files has write ports that correspond to the total number of write ports in the total register file structure. Writes are fully broadcast so that all of the separate and individual register files are coherent.

Abstract: A processor executes an instruction set including instructions in which a register specifier is implicitly derived, based on another register specifier. One technique for implicitly deriving a register specifier is to add or subtract one from a specifically-defined register specifier. Implicit derivation of a register specifier is selectively implemented for some opcodes. A decoder decodes instructions that use implicitly-derived register specifiers and reads the explicitly-defined register. The decoder generates pointers both to the explicitly-defined register and to the implicitly-derived register. In other embodiments, a pointer to registers within a register file includes an additional bit indicating that a register read is accompanied by a read of an implicitly-derived register.