Abstract: Techniques are disclosed for automatically determining whether a potential constraint set to be applied to a portion of a circuit are overconstrained. An environment circuit supplies inputs to the circuit portion. Embodiments of the invention recognize that if the environment circuit produces a set of outputs that contain a pattern that is not present in the potential constraint set, then the potential constraint set is overconstrained. A verification tool establishes the properties for the environmental circuit based on the potential constraint set. If the verification tool determines that the outputs produced by the environment circuit conflict with the properties of the environment circuit, then the verification tool concludes that the potential constraint set is overconstrained, because the environment circuit produces a pattern that is not present in the potential constraint set.

Abstract: A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where a simulation trace that causes the property to fail covers the cover directive. Thereafter, the property is evaluated, and dependent on the evaluation, the simulation trace is dumped and stored for subsequent exercising of the cover directive.

Abstract: A method for providing verification for a simulation design, including obtaining the simulation design comprising a programming language interface system call, encoding a target of the programming language interface system call into the simulation design to obtain a first modified simulation design, modifying the programming language interface system call to reference the target in the first modified simulation design to obtain a second modified simulation design, and verifying the second modified simulation design using a simulation testbench.

Abstract: A method for providing verification for a first simulation image involves removing nodes from the first simulation image to produce an optimized image and an optimized nodes image, simulating the optimized image, invoking the optimized nodes image if debugging is selected, reconstructing a second simulation image using the optimized image and the optimized nodes image, simulating the second simulation image to gather simulation data, and debugging the first simulation image using simulation data.

Abstract: A method for transforming a behavioral specification involves converting the behavioral specification into a diagram representation, converting a delay from the diagram representation if the behavioral specification comprises a delay, generating a compliant cycle diagram from the diagram representation, and deriving a cycle equivalent behavioral specification from the compliant cycle diagram.

Abstract: A system for tracing a simulation design involves an encoded assertion asserting a value of a node of the simulation design at a point in a simulation, a fanin cone detection facility configured to obtain a fanin cone for the encoded assertion, a waveform trace facility configured to obtain waveform data including a history of signal values for the node, and a simulation toolkit configured to obtain node data using the fanin cone and the waveform data.

Abstract: A method for providing verification for a simulation design involves analyzing a simulation design using a testbench comprising a rapid bug detection tool, and if a bug is detected, adding a bug isolation tool to the testbench, and isolating and eliminating the bug using the testbench comprising the bug isolation tool.

Abstract: The invention provides a method for detecting and isolating software bugs and generating a minimal set of stimuli to reproduce the bugs. The present invention utilizes a recursive algorithm to compare the output of successively smaller software blocks of a program in development to a verified output sample. The smallest software blocks which are found to contain a bug are isolated. For each of these isolated blocks, the smallest input vector is determined such that the application of this vector to the block expresses the bug. The present invention utilizes a separate recursive algorithm to determine these minimal vectors.

Abstract: A system and method for processing a variable looping statement into a constant looping statement to enable loop unrolling. A lower bound and an upper bound of the loop index within the variable looping statement are determined. A constant looping statement is then formed using the lower bound and upper bound to define a range over which the loop index varies within the constant looping statement. The constant looping statement further includes a conditional statement that reflects conditions in the initial expression and/or the exit expression of the variable looping statement. The conditional statement controls execution of the body of the generated constant looping statement, which includes the body from the original variable looping statement. Loop unrolling may then be performed on the generated constant looping statement.

Abstract: A method for dynamically customizing object code for simulation includes obtaining a statically generated object (SGO) and a first test vector, segmenting the SGO with a marker node to generate a segmented SGO comprising a plurality of SGO segments, generating a first simulation profile using the segmented SGO and the first test vector, locating a first unexercised segment of the plurality of SGO segments using the first simulation profile, and generating a first reduced SGO by removing the first unexercised segment from the segmented SGO.

Abstract: A method for dynamically customizing object code for simulation includes obtaining a statically generated object (SGO) and a first test vector, segmenting the SGO with a marker node to generate a segmented SGO comprising a plurality of SGO segments, generating a first simulation profile using the segmented SGO and the first test vector, locating a first unexercised segment of the plurality of SGO segments using the first simulation profile, and generating a first reduced SGO by removing the first unexercised segment from the segmented SGO.

Abstract: A method for transforming a behavioral specification involves converting the behavioral specification into a diagram representation, converting a delay from the diagram representation if the behavioral specification comprises a delay, generating a compliant cycle diagram from the diagram representation, and deriving a cycle equivalent behavioral specification from the compliant cycle diagram.

Abstract: A system and method for processing a variable looping statement into a constant looping statement to enable loop unrolling. A lower bound and an upper bound of the loop index within the variable looping statement are determined. A constant looping statement is then formed using the lower bound and upper bound to define a range over which the loop index varies within the constant looping statement. The constant looping statement further includes a conditional statement that reflects conditions in the initial expression and/or the exit expression of the variable looping statement. The conditional statement controls execution of the body of the generated constant looping statement, which includes the body from the original variable looping statement. Loop unrolling may then be performed on the generated constant looping statement.

Abstract: One embodiment of the present invention provides a system that facilitates representing a shape within a layout of an integrated circuit using a Boolean expression. The system operates by first receiving a representation of the shape and then converting the representation of the shape into a Boolean expression that is formed using a Boolean coordinate system expressed in a two-dimensional Gray code. The system then performs operations on the shape by performing Boolean operations on the Boolean expression for the shape.

Abstract: One embodiment of the present invention provides a system that facilitates representing a shape within a layout of an integrated circuit using a Boolean expression. The system operates by first receiving a representation of the shape and then converting the representation of the shape into a Boolean expression that is formed using a Boolean coordinate system expressed in a two-dimensional Gray code. The system then performs operations on the shape by performing Boolean operations on the Boolean expression for the shape.

Abstract: Based upon a circuit design, a system generates a plurality of seed circuits. An initial circuit constraint is used to generate a plurality of constraints sets, one for each seed circuit. The plurality of seed circuits and the corresponding constraint sets are distributed to a plurality of processors. In parallel, the processors execute a design software application to generate a plurality of candidate circuits based on the constraints and the seed circuits. The best candidate of the plurality of candidate circuits may be used for additional iterations in the design process.

Abstract: The invention provides a method for detecting and isolating software bugs and generating a minimal set of stimuli to reproduce the bugs. The present invention utilizes a recursive algorithm to compare the output of successively smaller software blocks of a program in development to a verified output sample. The smallest software blocks which are found to contain a bug are isolated. For each of these isolated blocks, the smallest input vector is determined such that the application of this vector to the block expresses the bug. The present invention utilizes a separate recursive algorithm to determine these minimal vectors.

Abstract: Based upon a circuit design, a system generates a plurality of subdesigns. An initial circuit constraint is used to generate a plurality of constraints, one for each subdesign. The plurality of subdesigns and the corresponding constraints are distributed to a plurality of processors. In parallel, the processors execute a design software application to generate a plurality of candidate circuits based on the constraints and the subdesigns. The best candidate of the plurality of candidate circuits may be used for additional iterations in the design process.