Abstract: Structure is disclosed for a non-blocking SAS architecture utilizing virtual connections between SAS devices. One embodiment comprises a SAS expander. The SAS expander comprises a plurality of physical links (PHYs) and a Virtual Connection Manager (VCM) coupled with the plurality of PHYs. The VCM exchanges information over a plurality of concurrently established virtual pathways between a first PHY of the plurality of PHYs and a second PHY of the plurality of PHYs.

Abstract: Systems and methods presented herein provide for tunneling PCIe data through a SAS domain. a data system includes a SAS expander, a PCIe target device coupled to the expander, and a SAS controller communicatively coupled to a host system and the expander. The controller is operable to open a connection with the expander via the SAS protocol, and to transport packet data between the target device and the host system through the connection via the PCIe protocol. For example, the controller and the expander may be operable to buffer packets of data in the connection. The controller may issue a number of the data packets to be transferred in the connection. Then, the issued number of data packets are transported between the target device and the host system through the connection via the PCIe protocol.

Abstract: Methods and structure for local reconnect attempts via a Serial Attached Small Computer System Interface (SAS) expander. The system includes a SAS expander, which includes a physical link (PHY) that is able to transmit an OPEN Address Frame (OAF) to a coupled SAS device, and to receive an OPEN_REJECT (RETRY) from the coupled device in response to the OAF. The SAS expander also includes a controller that is able to block transmission of the OPEN_REJECT (RETRY) out of the expander in order to preserve a signaling pathway established for the OAF, and to retransmit the OAF to the coupled device via the PHY.

Abstract: Methods and structure for dwell timers in Serial Attached Small Computer System Interface (SAS) devices. An exemplary system includes a SAS end device. The SAS end device includes a physical link (PHY) operable to receive an OPEN Address Frame (OAF) from a coupled SAS device. The SAS end device also includes a controller. The controller is able to determine that the end device is presently unable to service a connection, and to wait a period of time for a dwell timer to expire. The controller is also able to service the connection by sending an OPEN_ACCEPT response if the end device becomes able to service the connection before the dwell timer expires, and to send an OPEN_REJECT (RETRY) response if the end device does not become able to service the connection before the dwell timer expires.

Abstract: Systems and methods presented herein provide for coupling a storage controller to a plurality of different storage device types. One embodiment of the storage controller includes an interface operable to communicatively couple to a storage device. The storage controller also includes a processor operable to select between hardware protocol detection of the storage device and firmware protocol detection of the storage device, and to detect a protocol of the storage device when the storage device communicatively couples to the interface according to the selected protocol detection. The storage controller then selects a protocol to process input/output requests from a host based on the detected protocol of the storage device.

Abstract: Systems and methods presented herein provide for coupling a storage controller to a plurality of different storage device types. One embodiment of the storage controller includes an interface operable to communicatively couple to a storage device. The storage controller also includes a processor operable to select between hardware protocol detection of the storage device and firmware protocol detection of the storage device, and to detect a protocol of the storage device when the storage device communicatively couples to the interface according to the selected protocol detection. The storage controller then selects a protocol to process input/output requests from a host based on the detected protocol of the storage device.

Abstract: Systems and methods presented herein provide for tunneling PCIe data through a SAS domain. a data system includes a SAS expander, a PCIe target device coupled to the expander, and a SAS controller communicatively coupled to a host system and the expander. The controller is operable to open a connection with the expander via the SAS protocol, and to transport packet data between the target device and the host system through the connection via the PCIe protocol. For example, the controller and the expander may be operable to buffer packets of data in the connection. The controller may issue a number of the data packets to be transferred in the connection. Then, the issued number of data packets are transported between the target device and the host system through the connection via the PCIe protocol.

Abstract: The invention may be embodied in a SAS expander with register bits within Phys associated with I/O devices. Setting and unsetting the register bit in the Phy associated with a particular physical or logical device allows I/O traffic to be blocked and unblocked, as desired, to the selected physical or logical devices. In a particular embodiment, when the register bit is set to a blocking state, an OPEN request that comes in on the SAS link is rejected using OPEN_REJECT (RETRY). Phy register bits may be provided for multiple different SAS protocols that can be controlled individually for each attached SAS device. The Phy register bit may also be used to reject only SAS connection requests that attempt to leave a particular SAS link.

Abstract: Structure is disclosed for a non-blocking SAS architecture utilizing virtual connections between SAS devices. One embodiment comprises a SAS expander. The SAS expander comprises a plurality of physical links (PHYs) and a Virtual Connection Manager (VCM) coupled with the plurality of PHYs. The VCM exchanges information over a plurality of concurrently established virtual pathways between a first PHY of the plurality of PHYs and a second PHY of the plurality of PHYs.

Abstract: A method for back-off retry with priority routing includes routing a data transfer between an input of a single, cohesive SAS expander and an output of the SAS expander via at least one inter-expander link (IEL), the expander including a first SAS expander and at least one additional SAS expander. The method includes routing a first OPEN request on a direct path through the first SAS expander to a port of a device and routing a second OPEN request on an alternate path from the first SAS expander and through a second SAS expander to the port of the device. The method further includes, upon determination of a failed link or a busy link, re-routing the data transfer from the second SAS expander to the first SAS expander or a third SAS expander, or retrying the data transfer through the second SAS expander.

Abstract: The invention may be embodied in a SAS expander with register bits within Phys associated with I/O devices. Setting and unsetting the register bit in the Phy associated with a particular physical or logical device allows I/O traffic to be blocked and unblocked, as desired, to the selected physical or logical devices. In a particular embodiment, when the register bit is set to a blocking state, an OPEN request that comes in on the SAS link is rejected using OPEN_REJECT (RETRY). Phy register bits may be provided for multiple different SAS protocols that can be controlled individually for each attached SAS device. The Phy register bit may also be used to reject only SAS connection requests that attempt to leave a particular SAS link.

Abstract: An expander device and method for transmitting serial input/output (SIO) data between an initiator device and a plurality of target devices. The expander device includes a processor/controller configured to receive a master data stream from an initiator device and to transmit a returning master data stream to the initiator device. The expander device includes a plurality of target master ports coupled to the processor/controller and configured to transmit split data streams to corresponding target devices coupled thereto and to receive returning split data streams from the target devices. The processor/controller splits the master data stream, based on its data, into a plurality of split data streams, and directs the split data streams to the target master ports based on the data in the split data streams. The processor/controller also assembles a plurality of returning split data streams into the returning master data stream and transmits the returning master data stream to the initiator device.

Abstract: An input port is assigned to a SAS expander device. An output port is assigned to the SAS expander device. The output port and the input port are defined to be paired with each other as a primary subtractive port. Only a SAS initiator address is programmed in the route table of the SAS expander. An OPEN command is sent out the output port upon receiving the OPEN command into the input port if the DEST of the OPEN command is not a direct attached device of the SAS expander device and the DEST is not in the route table of the SAS expander device. An OPEN command is sent out the input port upon receiving the OPEN command into the output port if the DEST of the OPEN command is not a direct attached device of the SAS expander device and the DEST is not in the route table of the SAS expander device.

Abstract: An expander device and method for transmitting serial input/output (SIO) data between an initiator device and a plurality of target devices. The expander device includes a processor/controller configured to receive a master data stream from an initiator device and to transmit a returning master data stream to the initiator device. The expander device includes a plurality of target master ports coupled to the processor/controller and configured to transmit split data streams to corresponding target devices coupled thereto and to receive returning split data streams from the target devices. The processor/controller splits the master data stream, based on its data, into a plurality of split data streams, and directs the split data streams to the target master ports based on the data in the split data streams. The processor/controller also assembles a plurality of returning split data streams into the returning master data stream and transmits the returning master data stream to the initiator device.

Abstract: Methods and systems for encoding and/or decoding digital signals representing serial attached SCSI (SAS) out of band (OOB) signals exchanged over an optical communication between two SAS devices. A SAS OOB signal to be transmitted from a first SAS device to a second SAS device is first encoded as a digitally encoded signal representing the analog SAS OOB signal and then transmitted over an optical communication medium to another SAS device. A receiving SAS device coupled to an optical communication medium decodes a received digitally encoded signal to detect a received, encoded SAS OOB signal and processes the received SAS OOB signal when receipt is detected. The digitally encoded signal may comprise an idle word portion and a burst word portion to represent various SAS OOB signals. Further, the digitally encoded signal may be precomputed in a variety of disparity forms and stored in a memory for lookup and retrieval.

Abstract: Apparatus and methods for full address resolution in a zoning SAS expander. A single memory circuit is used in a zoning SAS expander to store zone information associated with the SAS address (e.g., WWN) of devices exchanging information through the expander. The source and destination addresses in a received SAS frame are used as inputs to the memory circuit to generate outputs of the memory circuit representing the source and destination zone group identifiers. These outputs are then applied to the zone permission table to determine the zoning permission for forwarding the frame through the expander. Pipelined logic within the expander sequences the operations of the memory circuit and the zone permissions table to account for clock cycle delays in processing of each. In one exemplary embodiment, the memory circuit is a content addressable memory (CAM). In another exemplary embodiment, the CAM also includes port routing information.

Abstract: Methods and systems for encoding and/or decoding digital signals representing serial attached SCSI (SAS) out of band (OOB) signals exchanged over an optical communication between two SAS devices. A SAS OOB signal to be transmitted from a first SAS device to a second SAS device is first encoded as a digitally encoded signal representing the analog SAS OOB signal and then transmitted over an optical communication medium to another SAS device. A receiving SAS device coupled to an optical communication medium decodes a received digitally encoded signal to detect a received, encoded SAS OOB signal and processes the received SAS OOB signal when receipt is detected. The digitally encoded signal may comprise an idle word portion and a burst word portion to represent various SAS OOB signals. Further, the digitally encoded signal may be precomputed in a variety of disparity forms and stored in a memory for lookup and retrieval.

Abstract: Apparatus and methods for full address resolution in a zoning SAS expander. A single memory circuit is used in a zoning SAS expander to store zone information associated with the SAS address (e.g., WWN) of devices exchanging information through the expander. The source and destination addresses in a received SAS frame are used as inputs to the memory circuit to generate outputs of the memory circuit representing the source and destination zone group identifiers. These outputs are then applied to the zone permission table to determine the zoning permission for forwarding the frame through the expander. Pipelined logic within the expander sequences the operations of the memory circuit and the zone permissions table to account for clock cycle delays in processing of each. In one exemplary embodiment, the memory circuit is a content addressable memory (CAM). In another exemplary embodiment, the CAM also includes port routing information.

Abstract: An input port is assigned to a SAS expander device. An output port is assigned to the SAS expander device. The output port and the input port are defined to be paired with each other as a primary subtractive port. Only a SAS initiator address is programmed in the route table of the SAS expander. An OPEN command is sent out the output port upon receiving the OPEN command into the input port if the DEST of the OPEN command is not a direct attached device of the SAS expander device and the DEST is not in the route table of the SAS expander device. An OPEN command is sent out the input port upon receiving the OPEN command into the output port if the DEST of the OPEN command is not a direct attached device of the SAS expander device and the DEST is not in the route table of the SAS expander device.

Abstract: An apparatus comprising a first plurality of parallel switches and a second plurality of parallel switches. The first plurality of parallel switches may be configured to control a voltage on a first output pin. The second plurality of parallel switches may be configured to control a voltage on a second output pin. The first and second pluralities of parallel switches may be configured to provide rise time control of a differential waveform and be driven by a phased data signal.