Abstract: A thermal detection system (10) includes a focal plane array (12), a thermal isolation structure (14), and an integrated circuit substrate (16). Focal plane array (12) includes thermal sensors (28), each having an associated thermal sensitive element (30). Thermal sensitive element (30) is coupled with one side to infrared absorber and common electrode assembly (36) and on the opposite side to an associated contact pad (20) disposed on the integrated circuit substrate (16). Reticulation kerfs (52a, 52b) separate adjacent thermal sensitive elements (30a, 30b, 30c) by a distance at least half the average width (44, 46) of a single thermal sensitive element (30a, 30b, 30c). A continuous, non-reticulated optical coating (38) may be disposed over thermal sensitive elements (30a, 30b, 30c) to maximize absorption of thermal radiation incident to focal plane array (12).

Abstract: A hybrid thermal detector and method for producing same where the optical coating 32 of the hybrid thermal detector has elongated parallel thermal isolation stots 62 along one axis. The elongated parallel slots 62 improve the acuity, or MTF of the resultant image produced by the detector along one axis. The optical coating 32 may be corrugated, or elevated, in order to add structural support and allow mechanical compliance along the axis of the slots.

Abstract: A hybrid thermal detector (10, 110) includes a focal plane array (20, 120), a thermal isolation structure (40, 140), and an integrated circuit substrate (60, 160). The focal plane array (20, 120) includes thermal sensors (30, 130). The thermal isolation structure (40, 140) includes untrimmed mesa-type formations (44, 146, 148) and mesa strip conductors (42, 142, 144) that provide thermal isolation, signal transport, and structural support of the focal plane array (20, 120) when mounted on the integrated circuit substrate (60, 160). Hybrid thermal detector (10) includes a common electrode (28) which provides a bias voltage to all thermal sensors (30). Hybrid thermal detector (110) has electrically isolated thermal sensors (130), each thermal sensor (130) is supported by mesa strip conductors (142, 144), which provide a bias voltage to and receive a signal voltage from the thermal sensor (130).

Abstract: A hybrid thermal detector (10, 110) includes a focal plane array (20, 120), a thermal isolation structure (40, 140), and an integrated circuit substrate (60, 160). The focal plane array (20, 120) includes thermal sensors (30, 130). The thermal isolation structure (40, 140) includes untrimmed mesa-type formations (44, 146, 148) and mesa strip conductors (42, 142, 144) that provide thermal isolation, signal transport, and structural support of the focal plane array (20, 120) when mounted on the integrated circuit substrate (60, 160). Hybrid thermal detector (10) includes a common electrode (28) which provides a bias voltage to all thermal sensors (30). Hybrid thermal detector (110) has electrically isolated thermal sensors (130), each thermal sensor (130) is supported by mesa strip conductors (142, 144), which provide a bias voltage to and receive a signal voltage from the thermal sensor (130).

Abstract: A hybrid thermal detector (10, 110) includes a focal plane array (20, 120), a thermal isolation structure (40, 140), and an integrated circuit substrate (60, 160). The focal plane array (20, 120) includes thermal sensors (30, 130). The thermal isolation structure (40, 140) includes untrimmed mesa-type formations (44, 146, 148) and mesa strip conductors (42, 142, 144) that provide thermal isolation, signal transport, and structural support of the focal plane array (20, 120) when mounted on the integrated circuit substrate (60, 160). Hybrid thermal detector (10) includes a common electrode (28) which provides a bias voltage to all thermal sensors (30). Hybrid thermal detector (110) has electrically isolated thermal sensors (130), each thermal sensor (130) is supported by mesa strip conductors (142, 144), which provide a bias voltage to and receive a signal voltage from the thermal sensor (130).

Abstract: A thermal isolation structure (10) is disposed between a focal plane array and an integrated circuit substrate (12). The thermal isolation structure (10) includes a mesa-type formation (16) and a mesa strip conductor (18, 26) extending from the top of the mesa-type formation (16) to an associated contact pad (14) on the integrated circuit substrate (12). After formation of the mesa-type formation (16) and the mesa strip conductor (18, 26), an anisotropic etch using the mesa strip conductor (18, 26) as an etch mask removes excess mesa material to form trimmed mesa-type formation (24) for improved thermal isolation. Bump bonding material (20) may be deposited on mesa strip conductor (18, 26) and can also be used as an etch mask during the anisotropic etch. Thermal isolation structure (100) can include mesa-type formations (102), each with a centrally located via (110) extending vertically to an associated contact pad (104) of integrated circuit substrate (106).

Abstract: This is a new hybrid integrated circuit. The device may be an uncooled infrared detector, with the detector comprising: uncooled infrared elements on a first substrate; internal IC structures on a second substrate to be connected to the uncooled infrared elements: IC interlevel insulation on top of the internal IC structures: IC top level metal connections on top of the IC interlevel insulation: a protective overcoat over the IC top level metal and the IC interlevel insulation; a dry etch protective layer over the protective overcoat; thermal isolation mesas on the protective layer; and local interconnects over the thermal isolation mesas and the substrate, wherein the uncooled infrared detectors are connected to the internal IC structures through the local interconnects. In addition, the protective layer may include a photosensitive polyimide, a plasma deposited silicon dioxide (SiO.sub.2), a colloidal SiO.sub.2, a PMMA or a PIRL.

Abstract: This is a system and method of fabricating hybrid integrated circuits (IC). The method may comprise: forming internal IC structures on a substrate; forming IC interlevel insulation on top of the internal IC structures; forming IC top level metal connections on top of the IC interlevel insulation; depositing a protective overcoat over the IC top level metal and the IC interlevel insulation; depositing a dry etch protective layer over the protective overcoat; and dry etching the etch protective layer and the protective overcoat to expose portions of the IC top level metal. The deposition of the protective overcoat may include depositing silicon dioxide or silicon nitride. In addition, the deposition of the dry etch protective layer may include depositing a photosensitive polymide layer. Furthermore, the dry etching may include photolithography.

Abstract: A thermal isolation structure (10) is disposed between a focal plane array and an integrated circuit substrate (12). The thermal isolation structure (10) includes a mesa-type formation (16) and a mesa strip conductor (18, 26) extending from the top of the mesa-type formation (16) to an associated contact pad (14) on the integrated circuit substrate (12). After formation of the mesa-type formation (16) and the mesa strip conductor (18, 26), an anisotropic etch using the mesa strip conductor (18, 26) as an etch mask removes excess mesa material to form trimmed mesa-type formation (24) for improved thermal isolation. Bump bonding material (20) may be deposited on mesa strip conductor (18, 26) and can also be used as an etch mask during the anisotropic etch. Thermal isolation structure (100) can include mesa-type formations (102), each with a centrally located via (110) extending vertically to an associated contact pad (104) of integrated circuit substrate (106).

Abstract: A thermal detection system (10) includes a focal plane array (12), a thermal isolation structure (14), and an integrated circuit substrate (16). Focal plane array (12) includes thermal sensors (28), each having an associated thermal sensitive element (30). Thermal sensitive element (30) is coupled with one side to infrared absorber and common electrode assembly (36) and on the opposite side to an associated contact pad (20) disposed on the integrated circuit substrate (16). Reticulation kerfs (52a, 52b) separate adjacent thermal sensitive elements (30a, 30b, 30c) by a distance at least half the average width (44, 46) of a single thermal sensitive element (30a, 30b, 30c). A continuous, non-reticulated optical coating (38) may be disposed over thermal sensitive elements (30a, 30b, 30c) to maximize absorption of thermal radiation incident to focal plane array (12).

Abstract: A thermal detection system (10, 110, 210) includes a focal plane array (20, 120, 220), a thermal isolation structure (40, 140, 240), and an integrated circuit substrate (60, 160, 260). The focal plane array (20, 120, 220) includes a plurality of thermal sensors (30, 130, 230). The thermal isolation structure (40, 140, 240) includes mesa-type formations (44, 146, 148, 244) and bridge structures (42, 142, 144, 242) that provide thermal isolation, signal transport, and structural support of the focal plane array (20, 120, 220) when mounted on the integrated circuit substrate (60, 160, 260). Thermal detection system (10) includes an infrared absorber and common electrode assembly (22) which provides a bias voltage to all thermal sensors (30). Thermal detection system (110) has a plurality of electrically isolated thermal sensors (130), each thermal sensor (130) is supported by bridge structures (142, 144), which provide a bias voltage to and receive a signal voltage from the thermal sensor (130).