Abstract: A pre-drilled hole, providing a passageway between an upper and a lower surface of a printed circuit board layer, receives a passive component, for example a resistor or a capacitor. In one embodiment the component is cylindrical, with an electrically conductive contact point at each end. The hole diameter is approximately the same as the diameter of the cylindrical component. The hole is similar to a via in a printed circuit board, except that the hole is not plated through (such would cause an electrical short). Electrically conductive lines are provided to the openings of the hole on the upper and the lower surfaces of the PCB. The area of the exposed end of the cylindrical component and the termination of the conducting line is less than the area of a surface mounted component equivalent to the cylindrical component.

Abstract: The die pad crack absorption integrated circuit chip fabrication system and method of the present invention minimizes the spread of cracks between layers of an integrated circuit chip. During an integrated circuit chip fabrication process relatively elastic material is deposited in modular elastic filler blocks located between intermetal oxide (IMO) layers of an integrated circuit chip. The modular elastic filler blocks comprise material with a lesser elastic modulous than the surrounding IMO material. These elasticity characteristics and modular configuration of the modular elastic filler blocks results in the modular elastic filler blocks being more flexible than adjacent materials and having a greater capacity to dissipate stress energy that propels cracking forces through layers of an integrated chip. By absorbing the stress energy, the modular elastic filler blocks reduce the spread of crack through the layers of an integrated chip.

Abstract: Disclosed is a semiconductor chip and method for making a semiconductor chip having strategically placed composite metallization. The semiconductor chip includes a topmost metallization layer that defines a plurality of patterned features including a plurality of input/output metallization pads for receiving an associated plurality of gold bonding wires. An inter-metal oxide layer that is defined under the topmost metallization layer. The semiconductor chip further includes an underlying metallization layer that is defined under the inter-metal oxide layer in order to electrically isolate the topmost metallization layer from the underlying metallization layer. The underlying metallization has a plurality of patterned features, and portions of the plurality of patterned features lie at least partially in locations that are underlying the plurality of input/output metallization pads.