Patents by Inventor William kwei-cheung Lam
William kwei-cheung Lam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9594524Abstract: A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (SSD)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (ALU). The ALU may be resident in one or both of flash memory chips or the SSD controller. When resident in the flash memory chips, a single ALU or multiple ALUs may be used. For example, a single ALU may be assigned to one, some, or each block of flash memory within the flash memory chip. As another example, an ALU may be assigned to a sub-block construct, such as to each bit line in the block. Having ALUs resident in the SSD enables more processing to be performed within the SSD and reduces the need to transmit data outside of the SSD for processing.Type: GrantFiled: May 25, 2016Date of Patent: March 14, 2017Assignee: SanDisk Technologies LLCInventor: William Kwei-Cheung Lam
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Publication number: 20160266848Abstract: A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (SSD)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (ALU). The ALU may be resident in one or both of flash memory chips or the SSD controller. When resident in the flash memory chips, a single ALU or multiple ALUs may be used. For example, a single ALU may be assigned to one, some, or each block of flash memory within the flash memory chip. As another example, an ALU may be assigned to a sub-block construct, such as to each bit line in the block. Having ALUs resident in the SSD enables more processing to be performed within the SSD and reduces the need to transmit data outside of the SSD for processing.Type: ApplicationFiled: May 25, 2016Publication date: September 15, 2016Applicant: SanDisk Technologies LLCInventor: William Kwei-Cheung Lam
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Patent number: 9354824Abstract: A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (SSD)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (ALU). The ALU may be resident in one or both of flash memory chips or the SSD controller. When resident in the flash memory chips, a single ALU or multiple ALUs may be used. For example, a single ALU may be assigned to one, some, or each block of flash memory within the flash memory chip. As another example, an ALU may be assigned to a sub-block construct, such as to each bit line in the block. Having ALUs resident in the SSD enables more processing to be performed within the SSD and reduces the need to transmit data outside of the SSD for processing.Type: GrantFiled: January 8, 2016Date of Patent: May 31, 2016Assignee: SanDisk Technologies, Inc.Inventor: William Kwei-Cheung Lam
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Publication number: 20160124654Abstract: A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (SSD)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (ALU). The ALU may be resident in one or both of flash memory chips or the SSD controller. When resident in the flash memory chips, a single ALU or multiple ALUs may be used. For example, a single ALU may be assigned to one, some, or each block of flash memory within the flash memory chip. As another example, an ALU may be assigned to a sub-block construct, such as to each bit line in the block. Having ALUs resident in the SSD enables more processing to be performed within the SSD and reduces the need to transmit data outside of the SSD for processing.Type: ApplicationFiled: January 8, 2016Publication date: May 5, 2016Inventor: William Kwei-Cheung Lam
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Patent number: 9239691Abstract: A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (SSD)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (ALU). The ALU may be resident in one or both of flash memory chips or the SSD controller. When resident in the flash memory chips, a single ALU or multiple ALUs may be used. For example, a single ALU may be assigned to one, some, or each block of flash memory within the flash memory chip. As another example, an ALU may be assigned to a sub-block construct, such as to each bit line in the block. Having ALUs resident in the SSD enables more processing to be performed within the SSD and reduces the need to transmit data outside of the SSD for processing.Type: GrantFiled: July 31, 2015Date of Patent: January 19, 2016Assignee: SanDisk Technologies, Inc.Inventor: William Kwei-Cheung Lam
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Publication number: 20150347058Abstract: A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (SSD)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (ALU). The ALU may be resident in one or both of flash memory chips or the SSD controller. When resident in the flash memory chips, a single ALU or multiple ALUs may be used. For example, a single ALU may be assigned to one, some, or each block of flash memory within the flash memory chip. As another example, an ALU may be assigned to a sub-block construct, such as to each bit line in the block. Having ALUs resident in the SSD enables more processing to be performed within the SSD and reduces the need to transmit data outside of the SSD for processing.Type: ApplicationFiled: July 31, 2015Publication date: December 3, 2015Inventor: William Kwei-Cheung Lam
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Patent number: 9134925Abstract: A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (SSD)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (ALU). The ALU may be resident in one or both of flash memory chips or the SSD controller. When resident in the flash memory chips, a single ALU or multiple ALUs may be used. For example, a single ALU may be assigned to one, some, or each block of flash memory within the flash memory chip. As another example, an ALU may be assigned to a sub-block construct, such as to each bit line in the block. Having ALUs resident in the SSD enables more processing to be performed within the SSD and reduces the need to transmit data outside of the SSD for processing.Type: GrantFiled: March 27, 2015Date of Patent: September 15, 2015Assignee: SanDisk Technologies Inc.Inventor: William Kwei-Cheung Lam
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Patent number: 9003109Abstract: A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (SSD)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (ALU). The ALU may be resident in one or both of flash memory chips or the SSD controller. When resident in the flash memory chips, a single ALU or multiple ALUs may be used. For example, a single ALU may be assigned to one, some, or each block of flash memory within the flash memory chip. As another example, an ALU may be assigned to a sub-block construct, such as to each bit line in the block. Having ALUs resident in the SSD enables more processing to be performed within the SSD and reduces the need to transmit data outside of the SSD for processing.Type: GrantFiled: May 29, 2014Date of Patent: April 7, 2015Assignee: SanDisk Technologies, Inc.Inventor: William Kwei-Cheung Lam
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Patent number: 7080365Abstract: A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an executable form.Type: GrantFiled: March 29, 2002Date of Patent: July 18, 2006Assignee: Sun Microsystems, Inc.Inventors: Jeffrey M. Broughton, Liang T. Chen, William kwei-cheung Lam, Derek E. Pappas, Ihao Chen, Thomas M. McWilliams, Ankur Narang, Jeffrey B. Rubin, Earl T. Cohen, Michael W. Parkin, Ashley N. Saulsbury, Michael S. Ball
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Patent number: 7076416Abstract: A method for evaluating a logic state of a design node involves compiling a logic design to generate an annotated symbol table and a levelized design, obtaining a logic evaluation cost from the levelized design, locating a strategic node using the logic evaluation cost, marking the strategic node, and computing the logic state of the design node using the annotated symbol table, the strategic node, and the levelized design.Type: GrantFiled: March 25, 2002Date of Patent: July 11, 2006Assignee: Sun Microsystems, Inc.Inventors: Liang T. Chen, William kwei-cheung Lam, Thomas M. McWilliams
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Patent number: 7036114Abstract: A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.Type: GrantFiled: March 29, 2002Date of Patent: April 25, 2006Assignee: Sun Microsystems, Inc.Inventors: Thomas M. McWilliams, Jeffrey B. Rubin, Derek E. Pappas, Oyekunle A. Olukotun, Jeffrey M. Broughton, David R. Emberson, William kwei-cheung Lam, Liang T. Chen, Ihao Chen, Earl T. Cohen, Michael W. Parkin
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Publication number: 20030188299Abstract: A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an executable form.Type: ApplicationFiled: March 29, 2002Publication date: October 2, 2003Inventors: Jeffrey M. Broughton, Liang T. Chen, William Kwei-Cheung Lam, Derek E. Pappas, Ihao Chen, Thomas M. McWilliams, Ankur Narang, Jeffrey B. Rubin, Earl T. Cohen, Michael W. Parkin, Ashley N. Saulsbury, Michael S. Ball
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Publication number: 20030040896Abstract: A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.Type: ApplicationFiled: March 29, 2002Publication date: February 27, 2003Inventors: Thomas M. McWilliams, Jeffrey B. Rubin, Derek E. Pappas, Oyekunle A. Olukotun, Jeffrey M. Broughton, David R. Emberson, William kwei-cheung Lam, Liang T. Chen, Ihao Chen, Earl T. Cohen, Michael W. Parkin
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Publication number: 20030037305Abstract: A method for evaluating a logic state of a design node involves compiling a logic design to generate an annotated symbol table and a levelized design and computing the logic state of the design node using the annotated symbol table and the levelized design.Type: ApplicationFiled: March 25, 2002Publication date: February 20, 2003Inventors: Liang T. Chen, William Kwei-Cheung Lam, Thomas M. McWilliams