Patents by Inventor William L. Bircher
William L. Bircher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9946319Abstract: The described embodiments include a computing device with a first entity and a second entity. In the computing device, a management controller dynamically sets a power-state limit for the first entity based on a performance coupling and a thermal coupling between the first entity and the second entity.Type: GrantFiled: October 21, 2013Date of Patent: April 17, 2018Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Indrani Paul, Manish Arora, Srilatha Manne, William L. Bircher
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Patent number: 9851777Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.Type: GrantFiled: January 2, 2014Date of Patent: December 26, 2017Assignee: Advanced Micro Devices, Inc.Inventors: Manish Arora, Indrani Paul, Yasuko Eckert, Nuwan S. Jayasena, Srilatha Manne, Madhu Saravana Sibi Govindan, William L. Bircher
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Patent number: 9760145Abstract: A system for saving the architectural state of a processor is described. The system performs a save state operation, which involves, for each sector in a set of sectors of the architectural state, determining whether the architectural state for the sector has already been saved to a memory, and saving the architectural state for the sector to the memory when the architectural state for the sector has not already been saved to the memory. Each sector in the set of sectors comprises a different and separate portion of the architectural state of the processor. The system determines whether the architectural state for a given sector has already been saved to the memory by checking a needs-rinsing flag for the given sector. The needs-rinsing flag for the given sector is asserted upon modifying the given sector and cleared following the save state operation.Type: GrantFiled: May 19, 2015Date of Patent: September 12, 2017Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Madhu S. S. Govindan, William L. Bircher
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Patent number: 9720487Abstract: Durations of power management states are predicted on a per-process basis. Some embodiments include storing, in one or more data structures associated with one or more processes, information indicating previous durations of a power management state associated with the process(es). Some embodiments also include predicting a subsequent duration of the power management state for the process(es) using information stored in the data structure(s).Type: GrantFiled: January 10, 2014Date of Patent: August 1, 2017Assignee: Advanced Micro Devices, Inc.Inventors: William L. Bircher, Madhu Saravana Sibi Govindan, Manish Arora, Michael J. Schulte, Nuwan S. Jayasena
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Publication number: 20160342354Abstract: A system for saving the architectural state of a processor is described. The system performs a save state operation, which involves, for each sector in a set of sectors of the architectural state, determining whether the architectural state for the sector has already been saved to a memory, and saving the architectural state for the sector to the memory when the architectural state for the sector has not already been saved to the memory. Each sector in the set of sectors comprises a different and separate portion of the architectural state of the processor. The system determines whether the architectural state for a given sector has already been saved to the memory by checking a needs-rinsing flag for the given sector. The needs-rinsing flag for the given sector is asserted upon modifying the given sector and cleared following the save state operation.Type: ApplicationFiled: May 19, 2015Publication date: November 24, 2016Inventors: Madhu S. S. Govindan, William L. Bircher
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Patent number: 9442557Abstract: The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.Type: GrantFiled: November 8, 2013Date of Patent: September 13, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Manish Arora, Nuwan S. Jayasena, Yasuko Eckert, Madhu Saravana Sibi Govindan, William L. Bircher, Michael J. Schulte, Srilatha Manne
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Patent number: 9317096Abstract: Methods, systems, and media are provided for power management. The power management includes, but is not limited to storing at a computer system a history of canceled entries into a low power state that interrupted a transition of the unit from an active mode to the low power state and disallowing transition of the unit into the low power state when a number of canceled entries indicated by the history of canceled entries exceeds a canceled entry threshold.Type: GrantFiled: December 18, 2012Date of Patent: April 19, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: William L. Bircher, Madhu Saravana Sibi Govindan, Brian E. Waldecker
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Patent number: 9110671Abstract: A method and apparatus for exiting a low power state based on a prior prediction is disclosed. An integrated circuit (IC) includes a functional unit configured to, during operation, cycle between intervals of an active state and intervals of an idle state. The IC also include a power management unit configured to place the functional unit in a low power state responsive to the functional unit entering the idle state. The power management unit is further configured to preemptively cause the functional unit to exit the low power state at a predetermined time after entering the low power. The predetermined time is based on a prediction of idle state duration made prior to entering the low power state. The prediction may be generated by a prediction unit, based on a history of durations of intervals in which the functional unit was in the idle state.Type: GrantFiled: December 21, 2012Date of Patent: August 18, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Yasuko Eckert, Srilatha Manne, William L Bircher, Mahdu S. S. Govindan, Michael J Schulte, Manish Arora
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Publication number: 20150198991Abstract: Durations of power management states are predicted on a per-process basis. Some embodiments include storing, in one or more data structures associated with one or more processes, information indicating previous durations of a power management state associated with the process(es). Some embodiments also include predicting a subsequent duration of the power management state for the process(es) using information stored in the data structure(s).Type: ApplicationFiled: January 10, 2014Publication date: July 16, 2015Applicant: Advanced Micro Devices, Inc.Inventors: William L. Bircher, Madhu Saravana Sibi Govindan, Manish Arora, Michael J. Schulte, Nuwan S. Jayasena
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Publication number: 20150185801Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.Type: ApplicationFiled: January 2, 2014Publication date: July 2, 2015Applicant: Advanced Micro Devices, Inc.Inventors: Manish Arora, Indrani Paul, Yasuko Eckert, Nuwan S. Jayasena, Srilatha Manne, Madhu Saravana Sibi Govindan, William L. Bircher
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Patent number: 8959372Abstract: An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.Type: GrantFiled: June 17, 2013Date of Patent: February 17, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Branover, Maurice B Steinman, William L Bircher
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Publication number: 20140362518Abstract: Various computing devices and methods of thermally managing the same are disclosed. In one aspect, an apparatus is provided that includes a case and a first sensor in the case. a case and a first sensor in the case. The first sensor is operable to generate an output in response to sensing contact with a body part of a user. The computing device manages thermal behavior of the computing device responsive to the output.Type: ApplicationFiled: June 10, 2013Publication date: December 11, 2014Inventors: Wei Huang, William L. Bircher
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Publication number: 20140281592Abstract: A method, system and computer-readable medium for allocating power among computing resources are provided. The method calculates an activity level of a first computer resource. When the activity level is less than a threshold value, the method increases the power allocation to a second computing resource. When the activity level exceeds the threshold value, the method decreases the power allocation to the second computing resource.Type: ApplicationFiled: March 18, 2013Publication date: September 18, 2014Applicant: Advanced Micro Devices, Inc.Inventors: William L. BIRCHER, Donald W. Cherepacha, Adam N.C. Clark
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Publication number: 20140181553Abstract: A method and apparatus for idle phase prediction in integrated circuits is disclosed. In one embodiment, an integrated circuit (IC) includes a functional unit configured to cycle between intervals of an active state and an idle state. The IC further includes a prediction unit configured to record a history of idle state durations for a plurality of intervals of the idle state. Based on the history of idle state durations, the prediction unit is configured to generate a prediction of the duration of the next interval of the idle state. The prediction may be used by a power management unit to, among other uses, determine whether to place the functional unit in a low power (e.g., sleep) state.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Yasuko Eckert, Srilatha Manne, William L. Bircher, Mahdu S.S. Govindan, Michael J. Schulte
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Publication number: 20140181556Abstract: A method and apparatus for exiting a low power state based on a prior prediction is disclosed. An integrated circuit (IC) includes a functional unit configured to, during operation, cycle between intervals of an active state and intervals of an idle state. The IC also include a power management unit configured to place the functional unit in a low power state responsive to the functional unit entering the idle state. The power management unit is further configured to preemptively cause the functional unit to exit the low power state at a predetermined time after entering the low power. The predetermined time is based on a prediction of idle state duration made prior to entering the low power state. The prediction may be generated by a prediction unit, based on a history of durations of intervals in which the functional unit was in the idle state.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Yasuko Eckert, Srilatha Manne, William L. Bircher, Mahdu S.S. Govindan, Michael J. Schulte, Manish Arora
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Publication number: 20140173298Abstract: Methods, systems, and media are provided for power management. The power management includes, but is not limited to storing at a computer system a history of canceled entries into a low power state that interrupted a transition of the unit from an active mode to the low power state and disallowing transition of the unit into the low power state when a number of canceled entries indicated by the history of canceled entries exceeds a canceled entry threshold.Type: ApplicationFiled: December 18, 2012Publication date: June 19, 2014Applicant: ADVANCED MICRO DEVICES, INC.Inventors: William L. Bircher, Madhu Saravana Sibi Govindan, Brian E. Waldecker
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Publication number: 20140149772Abstract: The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.Type: ApplicationFiled: November 8, 2013Publication date: May 29, 2014Applicant: Advanced Micro Devices, Inc.Inventors: Manish Arora, Nuwan S. Jayasena, Yasuko Eckert, Madhu Saravana Sibi Govindan, William L. Bircher, Michael J. Schulte, Srilatha Manne
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Publication number: 20140143565Abstract: The described embodiments include a computing device with a first entity and a second entity. In the computing device, a management controller dynamically sets a power-state limit for the first entity based on a performance coupling and a thermal coupling between the first entity and the second entity.Type: ApplicationFiled: October 21, 2013Publication date: May 22, 2014Applicant: Advanced Micro Devices, Inc.Inventors: Indrani Paul, Manish Arora, Srilatha Manne, William L. Bircher
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Publication number: 20130283078Abstract: An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.Type: ApplicationFiled: June 17, 2013Publication date: October 24, 2013Inventors: Alexander Branover, Maurice B. Steinman, William L. Bircher
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Publication number: 20130262780Abstract: An apparatus and method to enable a fast cache shutdown is disclosed. In one embodiment, a cache subsystem includes a cache memory and a cache controller coupled to the cache memory. The cache controller is configured to, upon restoring power to the cache subsystem, inhibit writing of modified data exclusively into the cache memory.Type: ApplicationFiled: March 30, 2012Publication date: October 3, 2013Inventors: Srilatha Manne, William L. Bircher, Madhu Sarvana Sibi Govindan, James M. O'Connor, Michael J. Schulte