Patents by Inventor William L. Ditto

William L. Ditto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9276564
    Abstract: A nanomechanical device, operating as a reprogrammable logic gate, and performing fundamental logic functions such as AND/OR and NAND/NOR. The logic function can be programmed (e.g., from AND to OR) dynamically, by adjusting the operating parameters of the resonator. The device can access one of two stable steady states, according to a specific logic function; this operation is mediated by the noise floor which can be directly adjusted, or dynamically tuned via an adjustment of the underlying nonlinearity of the resonator, i.e., it is not necessary to have direct control over the noise floor. The demonstration of this reprogrammable nanomechanical logic gate affords a path to the practical realization of a new generation of mechanical computers.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: March 1, 2016
    Assignee: THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE NAVY
    Inventors: William L. Ditto, Pritiraj Mohanty, Sudeshna Sinha, Ardeshir R. Bulsara, Diego Guerra, Krishnamurthy Murali
  • Patent number: 8447407
    Abstract: Neuronal excitation and inhibition of the brain is tracked in the hippocampal CA1 network during a latent period, wherein biomarkers are observed which include a sustained increase in the firing rate of the excitatory postsynaptic field activity, paired with a subsequent decrease in the firing rate of the inhibitory postsynaptic field activity; the mean amplitude profiles of both fEPSP and fEPSP field potential activity during the latent period have characteristic shapes; both excitatory and inhibitory CA1 field activity firing rates are observed to follow a circadian rhythm that drifts during epileptogenesis; the circadian rhythms described are in-phase in controls and anti-phase during epileptogenesis; and the fEPSP rate drifts from a circadian rhythm to a greater extent than the fEPSP rate. An additional biomarker is a change in a circadian rhythm of core body temperature. Therapeutic measures can include thermal, chemical, or electrical modulation, in an open or closed loop process.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: May 21, 2013
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Sachin S. Talathi, Dong-Uk Hwang, William L. Ditto, Paul R. Carney, Mark Spano
  • Patent number: 8436637
    Abstract: A nanomechanical device, operating as a reprogrammable logic gate, and performing fundamental logic functions such as AND/OR and NAND/NOR. The logic function can be programmed (e.g., from AND to OR) dynamically, by adjusting the operating parameters of the resonator. The device can access one of two stable steady states, according to a specific logic function; this operation is mediated by the noise floor which can be directly adjusted, or dynamically tuned via an adjustment of the underlying nonlinearity of the resonator, i.e., it is not necessary to have direct control over the noise floor. The demonstration of this reprogrammable nanomechanical logic gate affords a path to the practical realization of a new generation of mechanical computers.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: May 7, 2013
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: William L. Ditto, Pritiraj Mohanty, Sudeshna Sinha, Ardeshir R. Bulsara, Diego N. Guerra, Krishnamurthy Murali
  • Patent number: 8250055
    Abstract: A dynamical search engine for searching a database is also provided. The dynamical search engine includes an array of nonlinear dynamical elements. The nonlinear dynamical element information items in a manner that confines the state of each element on a fixed point and uniquely encodes the information items. The dynamical search engine also includes a controller for controlling electrical signals supplied to elements of the array in a predetermined sequence. One supplied signal increases a state value of each element of the array by a quantity defining a search key that corresponds to a searched-for information item. A subsequently supplied signal updates the state value of each element of the array by performing a nonlinear folding of each state value based on a predetermined pivot.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: August 21, 2012
    Assignees: University of Florida Research Foundation, Inc., Control Dynamics, Inc.
    Inventors: William L. Ditto, Sudeshna Sinha, Abraham Miliotis
  • Patent number: 8091062
    Abstract: A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic gate type to a different logic gate type in response to one or more reference signals. The array also includes one or more additional logic gates.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: January 3, 2012
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: William L. Ditto, Krishnamurthy Murali, Sudeshna Sinha
  • Patent number: 7973566
    Abstract: A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: July 5, 2011
    Assignees: University of Florida Research Foundation, Inc., Control Dynamics, Inc.
    Inventors: William L. Ditto, Krishnamurthy Murali, Sudeshna Sinha, Abraham Miliotis
  • Publication number: 20110130797
    Abstract: Neuronal excitation and inhibition of the brain is tracked in the hippocampual CA1 network during a latent period, wherein biomarkers are observed which include a sustained increase in the firing rate of the excitatory postsynaptic field activity, paired with a subsequent decrease in the firing rate of the inhibitory postsynaptic field activity within the CA1 region of the hippocampus; the mean amplitude profiles of both fEPSP and fIPSP field potential activity during the latent period have characteristic shapes; both excitatory and inhibitory CA1 field activity firing rates are observed to follow a circadian rhythm that drifts during epileptogenesis; the circadian rhythms described are in-phase in controls and anti-phase during epileptogenesis; and the fEPSP rate drifts from a circadian rhythm to a greater extent than the fIPSP rate. An additional biomarker is a change in a circadian rhythm of core body temperature.
    Type: Application
    Filed: November 1, 2010
    Publication date: June 2, 2011
    Inventors: Sachin S. Talathi, Dong-Uk Hwang, William L. Ditto, Paul R. Carney, Mark Spano
  • Patent number: 7924059
    Abstract: A logic gate is adapted to implement logical expressions. The logic gate includes at least one input that is adapted to receive an input signal and at least one control signal. At least one of the input signal and the control signal is a noise signal. At least one output is adapted to produce an output signal. A nonlinear updater operates as a dynamically configurable element and produces multiple different logic gates as selected by the control signal based at least in part on the noise signal. The nonlinear updater is electrically coupled to the input and is also electrically coupled to the output. The nonlinear updates is configured to apply a nonlinear function to the input signal in response to the control signal to produce the output signal representing a logical expression being implemented by one of the multiple different logic gates on the input signal.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: April 12, 2011
    Assignees: University of Florida Research Foundation, Inc., Control Dynamics, Inc.
    Inventors: William L. Ditto, Krishnamurthy Murali, Sudeshna Sinha, Adi Bulsara
  • Publication number: 20110062986
    Abstract: A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value.
    Type: Application
    Filed: November 23, 2010
    Publication date: March 17, 2011
    Applicants: University of Florida Research Foundation, Inc., Control Dynamics, Inc.
    Inventors: William L. Ditto, Krishnamurthy Murali, Sudeshna Sinha, Abraham Miliotis
  • Patent number: 7863937
    Abstract: A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: January 4, 2011
    Assignees: University of Florida Research Foundation, Inc., Control Dynamics, Inc.
    Inventors: William L. Ditto, Krishnamurthy Murali, Sudeshna Sinha, Abraham Miliotis
  • Publication number: 20100318506
    Abstract: A dynamical search engine for searching a database is also provided. The dynamical search engine includes an array of nonlinear dynamical elements. The nonlinear dynamical element information items in a manner that confines the state of each element on a fixed point and uniquely encodes the information items. The dynamical search engine also includes a controller for controlling electrical signals supplied to elements of the array in a predetermined sequence. One supplied signal increases a state value of each element of the array by a quantity defining a search key that corresponds to a searched-for information item. A subsequently supplied signal updates the state value of each element of the array by performing a nonlinear folding of each state value based on a predetermined pivot.
    Type: Application
    Filed: December 5, 2007
    Publication date: December 16, 2010
    Applicants: Control Dynamics, Inc., University of Florida Research Foundation, Inc.
    Inventors: William L. Ditto, Sudeshna Sinha, Abraham Miliotis
  • Publication number: 20100219858
    Abstract: A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value.
    Type: Application
    Filed: February 27, 2009
    Publication date: September 2, 2010
    Applicants: University of Florida Research Foundation, Inc., Control Dynamics, Inc.
    Inventors: William L. Ditto, Krishnamurthy Murali, Sudeshna Sinha, Abraham Miliotis
  • Publication number: 20100219862
    Abstract: A logic gate is adapted to implement logical expressions. The logic gate includes at least one input that is adapted to receive an input signal and at least one control signal. At least one of the input signal and the control signal is a noise signal. At least one output is adapted to produce an output signal. A nonlinear updater operates as a dynamically configurable element and produces multiple different logic gates as selected by the control signal based at least in part on the noise signal. The nonlinear updater is electrically coupled to the input and is also electrically coupled to the output. The nonlinear updates is configured to apply a nonlinear function to the input signal in response to the control signal to produce the output signal representing a logical expression being implemented by one of the multiple different logic gates on the input signal.
    Type: Application
    Filed: February 27, 2009
    Publication date: September 2, 2010
    Applicants: University of Florida Research Foundation, Inc., Control Dynamics, Inc.
    Inventors: WILLIAM L. DITTO, Krishnamurthy Murali, Sudeshna Sinha, Adi Bulsara
  • Publication number: 20080278196
    Abstract: A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic gate type to a different logic gate type in response to one or more reference signals. The array also includes one or more additional logic gates.
    Type: Application
    Filed: July 16, 2008
    Publication date: November 13, 2008
    Inventors: WILLIAM L. DITTO, KRISHNAMURTHY MURALI, SUDESHNA SINHA
  • Patent number: 7415683
    Abstract: A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic gate type to a different logic gate type in response to one or more reference signals. The array also includes one or more additional logic gates.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: August 19, 2008
    Assignees: University of Florida Research Foundation, Inc., Control Dynamics, Inc.
    Inventors: William L. Ditto, Krishnamurthy Murali, Sudeshna Sinha
  • Patent number: 7109918
    Abstract: This invention exploits the synchronization properties of coupled, nonlinear oscillators arrays to perform power combining, beam steering, and beam shaping. This architecture utilizes interactions between nonlinear active elements to generate beam patterns. A nonlinear array integrates the signal processing concurrently with the transduction of the signal. This architecture differs fundamentally from passive transducer arrays in three ways: 1) the unit cells are nonlinear, 2) the array purposely couples the unit cells together, and 3) the signal processing (beam steering and shaping) is done via dynamic interactions between unit cells. The architecture extends to both 1- and 2-dimensional arrays.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: September 19, 2006
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Brian K. Meadows, Ted H. Heath, Joseph D. Neff, Edgar A. Brown, David W. Fogliatti, Visarath In, Paul Hasler, Steve P. DeWeerth, William L. Ditto, Robert A. York
  • Patent number: 7096437
    Abstract: A dynamically configurable logic gate can include a controller configured to provide a first threshold reference signal; an adder configured to sum the first threshold reference signal and at least one input signal to generate a summed signal; a chaotic updater configured to apply a nonlinear function to the summed signal; and a subtractor configured to determine an output signal by taking a difference between a second threshold reference signal and the processed summed signal from the chaotic updater. The logic gate can operate as one of a plurality of different logic gates responsive to adjusting at least one of the threshold reference signals.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: August 22, 2006
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: William L. Ditto, Krishnamurthy Murali, Sudeshna Sinha
  • Patent number: 6606526
    Abstract: An accessible parameter of a chaos embodying system of a physical or biological type is monitored by extraction of measurement data and recordation thereof on a return map as a dynamic representation of the system activity, from which the magnitude and timing of intervention is determined and applied to the system in order to sustain chaos behavior.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: August 12, 2003
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Mark L. Spano, William L. Ditto, Visarath In
  • Patent number: 5800459
    Abstract: A DC electric field is applied to brain tissue in parallel alignment with urons thereof during periods of brief duration while the tissue is undergoing epileptic activity. The electric field is controllably changed in polarity and magnitude to modify such epileptic activity based on data obtained by recording such activity through electrodes that are isopotentially aligned within the electric field imposed on a slice of the brain tissue.
    Type: Grant
    Filed: December 24, 1996
    Date of Patent: September 1, 1998
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Mark L. Spano, Steven J. Schiff, Bruce J. Gluckman, William L. Ditto
  • Patent number: 5797965
    Abstract: A DC electric field is applied to brain tissue in parallel alignment with urons thereof during periods of brief duration while the tissue is undergoing epileptic activity. The electrical field is controllably varied in magnitude to suppress such epilieptic activity.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: August 25, 1998
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Mark L. Spano, Steven J. Schiff, Bruce J. Gluckman, William L. Ditto