Abstract: A digital phase acquisition clock recovery circuit includes a digital phase-locked loop that employs a truth table decoder to set the actual delay through a plurality of individual delay elements to generate a plurality of clock phase signals approximately equally spaced in time over one reference clock cycle, and a data sampler circuit that generates a plurality of received data samples from an incoming data sample taken at the rising edge of the respective clock phase signals and synchronizes the data samples to reference clock on a bit period-by-bit period basis. A digital phase acquisition circuit includes an edge detector which evaluates the data samples over each bit period to detect the location of a transition between respective adjacent samples, wherein logic is employed to continually determine the "relative quality" of each data sample, based upon its sampling time being furthest from a detected edge transition.

Abstract: A dc-coupled receiver for a shared optical system includes an input feedback amplifier circuit which establishes a dc reference baseline voltage level for incoming packets of data. A pair of sample-and-hold circuits are connected in parallel to receive and sample signals from the feedback amplifier circuit when no data is being transmitted and at the initial edge of incoming packets of data. A voltage divider circuit receiving signals from the sample-and-hold circuits establishes a dc slicing level for each incoming packet of data. An output feedback circuit can be added to compensate for offset error without affecting the performance of the sample-and-hold circuitry.

Abstract: A circuit for controlling an extinction ratio of a laser whose temperature can change over time includes first and second feedback loops which monitor a LOW output power of the laser during a first frame training pulse and a HIGH laser output power during a second frame training pulse. The LOW power output is compared to a preset dynamic LOW power reference, and a LOW bias current applied to the laser is incrementally increased or decreased so as to keep this LOW power output toggling about this LOW reference. Similarly, the HIGH power output is compared to a HIGH power reference, and a modulation current for the laser is incrementally increased or decreased to keep the HIGH laser output power toggling about this HIGH reference. Preferably, the training pulse is sent once per frame thus enabling both the LOW and HIGH laser output powers to be kept constant regardless of whatever dynamic variables may change over time thus keeping the laser extinction ratio constant.

Abstract: A protocol for fiber-optic communication systems, or other communication systems based on transmission of unipolar pulses having wide dynamic range provides for information to be transmitted in packets having a predictable time slot for each transmitter. The receiver for such protocol has a first relatively long RC time constant mode conditioned for reception of data packets whose time of arrival is well predictable and a second relatively short RC time constant mode conditioned for reception of asynchronous randomly received packets. In the relatively long RC time constant mode, each packet includes a preamble having a first clamp interval in which no pulse is transmitted, and a second clamp interval in which a continual pulse is transmitted. A transducer on the receiver translates the packets of pulses into differential electronic signals on first and second outputs.

Abstract: A method and apparatus implementing the method are provided for controlling optical power output level of a laser diode modulated during a burst mode interval by digital data transitions within a shared logical bus optical communications network and over a predetermined thermal gradient. The method comprises the steps of: optically monitoring a component of the optical output power of the laser diode during each burst mode interval and converting the component into a control signal, establishing a reference signal and comparing the control signal with the established reference signal and for providing a logical condition from said comparison, generating a strobe signal from information related in time to the burst mode interval, storing the logical condition upon receipt of the strobe signal, integrating the stored logical condition over a time period to provide an integrated control signal, and regulating current flow through the laser diode in accordance with the integrated control signal.

Abstract: A protocol for fiber-optic communication systems, or other communication systems based on transmission of unipolar pulses having wide dynamic range provides for information to be transmitted in packets having a predictable time slot for each transmitter. The receiver for such protocol has a first relatively long RC time constant mode conditioned for reception of data packets whose time of arrival is well predictable and a second relatively short RC time constant mode conditioned for reception of asynchronous randomly received packets. In the relatively long RC time constant mode, each packet includes a preamble having a first clamp interval in which no pulse is transmitted, and a second clamp interval in which a continual pulse is transmitted. A transducer on the receiver translates the packets of pulses into differential electronic signals on first and second outputs.

Abstract: A transimpedance front end is provided for an optical receiver which includes a photodetector coupled optically to an optical fiber for receiving optical signals over the fiber and connected electrically to the front end. The front end comprises a buffer amplifier connected to the photodetector, a first amplifier selectively connected to the buffer through a first switch and through a first, high value feedback resistor in order to define a first mode low optical signal level amplifier configuration, a second amplifier selectively connected to the buffer through a second switch and through a second, switched low value resistor to define a second mode high optical signal level amplifier configuration, and an optical level sensing and switching control circuit connected to the photodetector for sensing incoming optical signal level and for switching between the first and second amplifier configurations as a function thereof.

Abstract: A method and apparatus implementing the method are provided for controlling optical power output level of a laser diode modulated during a burst mode interval by digital data transitions within a shared logical bus optical communications network and over a predetermined thermal gradient. The method comprises the steps of: optically monitoring a component of the optical output power of the laser diode during each burst mode interval and converting the component into a control signal, establishing a reference signal and comparing the control signal with the established reference signal and for providing a logical condition from said comparison, generating a strobe signal from information related in time to the burst mode interval, storing the logical condition upon receipt of the strobe signal, integrating the stored logical condition over a time period to provide an integrated control signal, and regulating current flow through the laser diode in accordance with the integrated control signal.

Abstract: Band gap voltage regulator employing a self-balancing bridge circuit for controlling current flow through two parallel branches. Voltage points in each branch are alternately sampled and applied to one input of a comparator in a delta modulator circuit. The output of the delta modulator circuit is applied to the other input of the comparator. The output of the comparator is applied to a control circuit which controls a current source in each of the two branches. The voltages at each voltage point are alternately compared with the voltage at the other input of the comparator, and the result is employed to control the current sources so that the voltages at both points are equalized despite any offset voltage in the comparator.

Abstract: A comparator circuit of one type, prior to this invention, had a reliability problem due to an undesirable conductive path, and had limited speed due to stray capacitances. Reliability is achieved through separate triodes for coupling an inverted storage pulse to a primary electrode of each of two triodes of a differential amplifier. Speed is achieved through coupling a transistor across the other primary electrodes of the differential amplifier, the transistor's gate electrode receiving a narrow pulse upon termination of the storage pulse.

Abstract: Color demodulating apparatus for a color television receiver. The chrominance signal is separated from other components of the composite video signal and sampled at the color subcarrier frequency to produce charges representative of the synchronously detected chrominance signal. The charges are applied to two CCD delay lines which introduce a delay differential at their outputs equal to the horizontal line period of the television receiver. The outputs of the CCD delay lines are combined in a summing network. Due to the interleaving principle present with standard NTSC signals the demodulated chrominance signals add and any unwanted high frequency luminance components cancel. The output of the summing network is lowpass filtered to produce a continuous color video signal which is free of cross-color effects.

Abstract: A comparator circuit having offset correction circuitry for use in an analog-to-digital converter. The first input of the comparator circuit is periodically connected to ground. The second input of the comparator circuit is connected through a capacitance to ground. The offset voltage generated within the comparator circuit can be considered as being present at the first input. When the offset voltage at the first input is greater than the voltage at the second input a fixed increment of electrical charge is added to the capacitance. When it is less, a fixed increment of electrical charge is subtracted from the capacitance. Thus, increments of electrical charge are accumulated in the capacitance producing a compensating voltage thereacross to correct for the offset voltage.

Abstract: Receiving apparatus for receiving and detecting binary encoded continuous wave RF signals. The binary signal is detected by a superregenerative detector. The detected signal and a DC reference voltage are applied to an amplifier which produces a signal corresponding to the detected signal but shifted to vary in amplitude about an axis at the DC reference voltage. The shifted signal and the DC reference voltage are applied to a comparator which produces an output signal at a predetermined voltage level when the shifted signal is greater than the DC reference voltage and at 0 volts when the shifted signal is less than the DC reference voltage. Thus a noise-free binary signal having sharply defined voltage transitions is obtained.

Abstract: A digital-to-analog converting apparatus having a plurality of stages arranged in a series. Each stage includes a latch for storing one of the bits of a digital input signal. Each stage includes a resistance, the resistances of the stages being connected in series. One end of the resistance in the first stage is connected to a reference voltage equal to the mid-point of the voltage range of the analog output signal to be produced. Constant current sources, of equal value in each stage, are connected to each end of the resistance and through a current switch to a constant current sink. The current switch is controlled by the outputs of the latch of the stage so that a constant current flows through the resistance in one direction or the other, increasing or decreasing the voltage applied to the next resistance in the series depending upon whether the stored bit is a logic 1 or a logic 0.

Abstract: An analog-to-digital converting apparatus having a plurality of stages arranged in series, each stage including a comparator. The positive input terminals of all the comparators are connected in common to the analog signal input terminal. The negative input terminal of the first comparator in the series is connected to a reference voltage equal to the mid-point of the voltage range of the analog input signals. Each stage except the last has a resistance connected between the negative input terminal of its comparator and that of the next comparator in the series. Constant current sources, of equal value in each stage, are connected to each end of the resistance and through a current switch to a constant current sink. The current switch is conrolled by the output of the comparator of the stage so that a constant current flows through the resistance in one direction or the other, increasing or decreasing the voltage at the negative input terminal of the next comparator in the series.

Abstract: Sensing apparatus for monitoring the passage of objects, including people, through a doorway. A source of radiant energy is positioned at one side of the doorway and two spaced-apart detectors are positioned at the opposite side to receive beams of radiant energy from the source. A receiver is connected to each detector and produces a signal indicating whether the beam of radiation from the source is impinging on its associated detector or is being blocked by a passing object. Logic circuitry responds to the signals from the receivers and produces a first or second output condition depending upon which beam from the source is the last one to be interrupted by a passing object.

Abstract: Variable phase shift apparatus employing two transistors having their bases connected together and their collectors connected together. The input terminal is coupled to the emitter of the first transistor. A phase control arrangement of a capacitance and a variable resistance in series is connected between the input terminal and ground. The juncture of the capacitance and the variable resistance is connected to the bases of both transistors. A phase control signal is present at this juncture. The collector current in the first transistor is in phase with the difference between the input signal and the phase control signal. The collector current in the second transistor is 180.degree. out of phase with the phase control signal. The two collector currents are combined by flowing through a common load resistance to produce an output signal which is the resultant of the collector currents in the two transistors.