Patents by Inventor William L. Guthrie

William L. Guthrie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200110704
    Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.
    Type: Application
    Filed: November 22, 2019
    Publication date: April 9, 2020
    Inventors: Sanjeev Ghai, Guy L. Guthrie, Stephen J. Powell, William J. Starke
  • Patent number: 10613792
    Abstract: In a data processing system implementing a weak memory model, a lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed. The lower level cache also receives, from the processor core, a barrier request that requests enforcement of ordering of memory access requests prior to the barrier request with respect to memory access requests after the barrier request. In response to the barrier request, the lower level cache enforces a barrier indicated by the barrier request with respect to a final paste-type request ending the memory move but not with respect to other copy-type requests and paste-type requests in the memory move.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, William J Starke, Derek E. Williams
  • Patent number: 10579527
    Abstract: A cache coherent data processing system includes at least non-overlapping first, second, and third coherency domains. A master in the first coherency domain of the cache coherent data processing system selects a scope of an initial broadcast of an interconnect operation from among a set of scopes including (1) a remote scope including both the first coherency domain and the second coherency domain, but excluding the third coherency domain that is a peer of the first coherency domain, and (2) a local scope including only the first coherency domain. The master then performs an initial broadcast of the interconnect operation within the cache coherent data processing system utilizing the selected scope, where performing the initial broadcast includes the master initiating broadcast of the interconnect operation within the first coherency domain.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Michael S. Siegel, William J. Starke, Jeffrey A. Stuecheli, Derek E. Williams
  • Publication number: 20190370198
    Abstract: A snooper of a processing unit connected to processing units via a system fabric receives a first single bus command in a bus protocol that allows sampling over the system fabric of the capability of snoopers to handle an interrupt and returns a first response indicating the capability of the snooper to handle the interrupt. The snooper, in response to receiving a second single bus command in the bus protocol to poll a first selection of snoopers for an availability status to service a criteria specified in the second single bus command, returns a second response indicating the availability of the snooper to service the criteria. The snooper, in response to receiving a third single bus command in the bus protocol to direct the snooper to handle the interrupt, assigns the interrupt to a particular processor thread of a respective selection of the one or more separate selections of processors threads distributed in the processing unit.
    Type: Application
    Filed: August 14, 2019
    Publication date: December 5, 2019
    Inventors: RICHARD L. ARNDT, FLORIAN AUERNHAMMER, WAYNE M. BARRETT, ROBERT A. DREHMEL, GUY L. GUTHRIE, MICHAEL S. SIEGEL, WILLIAM J. STARKE
  • Patent number: 10437725
    Abstract: A technique for operating a data processing system includes transitioning, by a cache, to a highest point of coherency (HPC) for a cache line in a required state without receiving data for one or more segments of the cache line that are needed. The cache issues a command to a lowest point of coherency (LPC) that requests data for the one or more segments of the cache line that were not received and are needed. The cache receives the data for the one or more segments of the cache line from the LPC that were not previously received and were needed.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Michael S. Siegel, William J. Starke, Jeffrey A. Stuecheli
  • Patent number: 10423550
    Abstract: A processing unit connected via a system fabric to multiple processing units calls a first single command in a bus protocol that allows sampling over the system fabric of the capability of snoopers distributed across the processing units to handle an interrupt. The processing unit, in response to detecting at least one first selection of snoopers with capability to handle the interrupt, calling a second single command in the bus protocol to poll the first selection of snoopers over the system fabric for an availability status. The processing unit, in response to detecting at least one second selection of snoopers respond with the available status indicating an availability to handle the interrupt, assigning a single snooper from among the second selection of snoopers to handle the interrupt by calling a third single command in the bus protocol.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard L. Arndt, Florian Auernhammer, Wayne M. Barrett, Robert A. Drehmel, Guy L. Guthrie, Michael S. Siegel, William J. Starke
  • Publication number: 20190220409
    Abstract: A cache coherent data processing system includes at least non-overlapping first, second, and third coherency domains. A master in the first coherency domain of the cache coherent data processing system selects a scope of an initial broadcast of an interconnect operation from among a set of scopes including (1) a remote scope including both the first coherency domain and the second coherency domain, but excluding the third coherency domain that is a peer of the first coherency domain, and (2) a local scope including only the first coherency domain. The master then performs an initial broadcast of the interconnect operation within the cache coherent data processing system utilizing the selected scope, where performing the initial broadcast includes the master initiating broadcast of the interconnect operation within the first coherency domain.
    Type: Application
    Filed: January 17, 2018
    Publication date: July 18, 2019
    Inventors: GUY L. GUTHRIE, MICHAEL S. SIEGEL, WILLIAM J. STARKE, JEFFREY A. STUECHELI, DEREK E. WILLIAMS
  • Patent number: 10331373
    Abstract: A data processing system includes at least one processor core each having an associated store-through upper level cache and an associated store-in lower level cache. In response to execution of a memory move instruction sequence including a plurality of copy-type instructions and a plurality of paste-type instructions, the at least one processor core transmits a corresponding plurality of copy-type and paste-type requests to its associated lower level cache, where each copy-type request specifies a source real address and each paste-type request specifies a destination real address. In response to receipt of each copy-type request, the associated lower level cache copies a respective data granule from a respective storage location specified by the source real address of that copy-type request into a non-architected buffer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, William J. Starke, Derek E. Williams
  • Patent number: 10101918
    Abstract: Systems and methods for generating hint information associated with a host command are disclosed. In one implementation, a processor of a host system determines whether the host system has initiated a procedure that will send a command to a non-volatile memory system. The processor analyzes at least one of metadata or payload data associated with the command to determine whether the processor is able to generate hint information associated with the at least one of metadata or payload data. The processor generates hint information based on the analysis of the at least one of metadata or payload data, sends the hint information to the non-volatile memory system, and sends the command to the non-volatile memory system.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: October 16, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Judah Gamliel Hahn, Joseph R. Meza, William L. Guthrie
  • Patent number: 9824007
    Abstract: Systems, methods and/or devices are used to enable enhancing data integrity to protect against returning old versions of data. In one aspect, the method includes (1) receiving a write request from a host that specifies write data for a set of logical block addresses in a logical address space of the host, (2) mapping the set of logical block addresses to a set of physical addresses corresponding to physical pages of the storage device, and (3) performing one or more operations for each logical block specified by the set of logical block addresses, including: (a) generating metadata for the logical block, the metadata including a version number for the logical block, (b) storing the metadata, including the version number, in a header of a physical page in which the logical block is stored, and (c) storing the version number in a version data structure.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: November 21, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Girish B. Desai, William L. Guthrie
  • Patent number: 9817752
    Abstract: Systems, methods and/or devices are used to enhance data integrity to protect against returning old versions of data. In one aspect, a method includes (1) receiving a write request from a host that specifies write data for a set of logical block addresses, (2) mapping, using a mapping table, the set of logical block addresses to a set of physical addresses, where the mapping table includes a plurality of subsets, and (3) performing operations for each subset of the mapping table that includes at least one entry corresponding to a logical block specified by the set of logical block addresses, including: (a) generating metadata for the subset, the metadata including a version number for the subset, (b) calculating a Cyclic Redundancy Check (CRC) checksum for the subset, and (c) storing the version number for the subset and the CRC checksum for the subset in a version data structure.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: November 14, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Girish B. Desai, William L. Guthrie
  • Publication number: 20160210045
    Abstract: Systems and methods for generating hint information associated with a host command are disclosed. In one implementation, a processor of a host system determines whether the host system has initiated a procedure that will send a command to a non-volatile memory system. The processor analyzes at least one of metadata or payload data associated with the command to determine whether the processor is able to generate hint information associated with the at least one of metadata or payload data. The processor generates hint information based on the analysis of the at least one of metadata or payload data, sends the hint information to the non-volatile memory system, and sends the command to the non-volatile memory system.
    Type: Application
    Filed: January 21, 2015
    Publication date: July 21, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Judah Gamliel Hahn, Joseph R. Meza, William L. Guthrie
  • Publication number: 20160147651
    Abstract: Systems, methods and/or devices are used to enhance data integrity to protect against returning old versions of data. In one aspect, a method includes (1) receiving a write request from a host that specifies write data for a set of logical block addresses, (2) mapping, using a mapping table, the set of logical block addresses to a set of physical addresses, where the mapping table includes a plurality of subsets, and (3) performing operations for each subset of the mapping table that includes at least one entry corresponding to a logical block specified by the set of logical block addresses, including: (a) generating metadata for the subset, the metadata including a version number for the subset, (b) calculating a Cyclic Redundancy Check (CRC) checksum for the subset, and (c) storing the version number for the subset and the CRC checksum for the subset in a version data structure.
    Type: Application
    Filed: February 24, 2015
    Publication date: May 26, 2016
    Inventors: Girish B. Desai, William L. Guthrie
  • Publication number: 20160147468
    Abstract: Systems, methods and/or devices are used to enable enhancing data integrity to protect against returning old versions of data. In one aspect, the method includes (1) receiving a write request from a host that specifies write data for a set of logical block addresses in a logical address space of the host, (2) mapping the set of logical block addresses to a set of physical addresses corresponding to physical pages of the storage device, and (3) performing one or more operations for each logical block specified by the set of logical block addresses, including: (a) generating metadata for the logical block, the metadata including a version number for the logical block, (b) storing the metadata, including the version number, in a header of a physical page in which the logical block is stored, and (c) storing the version number in a version data structure.
    Type: Application
    Filed: February 24, 2015
    Publication date: May 26, 2016
    Inventors: Girish B. Desai, William L. Guthrie
  • Patent number: 8949491
    Abstract: Buffer memory reservation techniques for use with NAND flash memory include dynamically reserving regions of the buffer memory, responsive to a read/write request. Where the read/write request includes a plurality of data transfer requests, following completion of a data transfer request, the reserved buffer space may be recycled for use in a further data transfer request or for other purposes. During fulfillment of a read request, a buffer region is reserved from a larger buffer pool for a time period significantly smaller than the time required to execute a sense operation associated with the read request. The reserved buffer region may be reused for unrelated processes during execution of the sense operation.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: February 3, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Gary Lin, Robert Jackson, Yoav Weinberg, William L. Guthrie, Girish B. Desai
  • Publication number: 20150019766
    Abstract: This disclosure provides examples of circuits, devices, systems, and methods for managing a buffer memory. Regions of the buffer memory are dynamically reserved, responsive to a read/write request. Where the read/write request includes a plurality of data transfer requests, following completion of a data transfer request, the reserved buffer space may be recycled for use in a further data transfer request or for other purposes. During fulfillment of a read request, a buffer region is reserved from a larger buffer pool for a time period significantly smaller than the time required to execute a sense operation associated with the read request. The reserved buffer region may be reused for unrelated processes during execution of the sense operation.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 15, 2015
    Inventors: Gary Lin, Robert Jackson, Yoav Weinberg, William L. Guthrie, Girish B. Desai
  • Publication number: 20140038501
    Abstract: A polishing pad assembly for a chemical mechanical polishing apparatus includes a polishing pad having a polishing surface and a surface opposite the polishing surface for attachment to a platen, and a solid light-transmissive window formed in the polishing pad. The light-transmissive window is more transmissive to light than the polishing pad. The light-transmissive window has a light-diffusing bottom surface.
    Type: Application
    Filed: October 10, 2013
    Publication date: February 6, 2014
    Applicant: Applied Materials, Inc.
    Inventors: Manoocher Birang, Allan Gleason, William L. Guthrie
  • Publication number: 20080227367
    Abstract: A method of polishing a substrate includes holding the substrate on a polishing pad with a polishing head, wherein the polishing pad is supported by a platen, creating relative motion between the substrate and the polishing pad to polish a side of the substrate, generating a light beam and directing the light beam towards the substrate to cause the light beam to impinge on the side of the substrate being polished. Light reflected from the substrate is at a detector to generate an interference signal. A measure of uniformity is computed from the interference signal.
    Type: Application
    Filed: August 14, 2007
    Publication date: September 18, 2008
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Manoocher Birang, Allan Gleason, William L. Guthrie
  • Publication number: 20080098170
    Abstract: A desired cache size in a disk drive is established, and no reordering algorithm is performed on commands in the cache until the desired size is reached. An optimal subset size is also established. Then, an optimization algorithm is performed on all commands in the cache, with only the commands in the optimal subset being output for execution. The cache is refilled to the desired size, and the process is repeated.
    Type: Application
    Filed: October 23, 2006
    Publication date: April 24, 2008
    Inventors: William L. Guthrie, Joe-Ming Cheng, Nyles Norbert Heise
  • Patent number: 7255629
    Abstract: The polishing pad for a chemical mechanical polishing apparatus, and a method of making the same. The polishing pad has a covering layer with a polishing surface and a backing layer which is adjacent to the platen. A first opening in the covering layer with a first cross-sectional area and a second opening in the backing layer with a second, different cross-sectional area form an aperture through the polishing pad. A substantially transparent polyurethane plug is positioned in the aperture, and an adhesive material fixes the plug in the aperture.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: August 14, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Manoocher Birang, Allan Gleason, William L. Guthrie