Abstract: A network device routes data packets by storing the packets in a switching memory as a function of a destination address of the packet. The switching memory comprises switching memory queues that are mapped to ports of the device. A header of a received packet is examined to determine the network destination address to which it is to be routed, and a destination queue is assigned to the packet based on the destination address. Thereafter, the packet is divided into cells, and the cells are written to contiguous locations in the destination queue.

Abstract: A network device routes data packets by storing the packets in a switching memory as a function of a destination address of the packet. The switching memory comprises switching memory queues that are mapped to ports of the device. A header of a received packet is examined to determine the network destination address to which it is to be routed, and a destination queue is assigned to the packet based on the destination address. Thereafter, the packet is divided into cells, and the cells are written to contiguous locations in the destination queue.

Abstract: A router including a lookup execution unit including a plurality of stages, a forwarding table memory arranged in hierarchy including addressable sectors, blocks, and entries, and a crossbar having an address crossbar for selectively coupling one of the plurality of stages to a sector of the memory so that data from the sector can be read. In one example, any one of the stages of the plurality of stages may be selectively and dynamically coupled with any one of the sectors of the forwarding table memory for providing an address to a particular sector of the memory to read data therefrom.

Abstract: A method for routing and switching data packets from one or more incoming links to one or more outgoing links of a router. The method comprises receiving a data packet from the incoming link, assigning at least one outgoing link to the data packet based on the destination address of the data packet, and after the assigning operation, storing the data packet in a switching memory based on the assigned outgoing link. The data packet extracted from the switching memory, and transmitted along the assigned outgoing link. The router may include a network processing unit having one or more systolic array pipelines for performing the assigning operation.

Abstract: A method for a router having a routing table and a forwarding table. In an embodiment, the method includes creating an entry for use in the forwarding table, the entry corresponding to multiple entries of the routing table. The entry may correspond to a set of entries of the routing table which specify overlapping IP addresses and a same next hop router, in one example. In another example, the entry may be an aggregate entry corresponding to a set of entries of the routing table which specify the same next hop router.

Abstract: Methods of routing and switching a packet from an incoming link to an outgoing link of a router. In one example, the method includes assigning a destination queue to the packet, determining if the router is implemented in a scaled-down configuration, remapping the destination queue to one or more remapped destination queues, and storing the packet in the one or more remapped destination queues. In one embodiment, the method may also include requesting a packet from the destination queue, translating the request to the remapped destination queue, and transmitting the packet from the remapped destination queue.

Abstract: A method and system for determining an output port upon which to transmit a packet in a router having a plurality of output ports adapted to be coupled with an adjacent router. In one embodiment, a list is created of output ports that are coupled with the adjacent router, and the list is modified based on network traffic. A port is selected from the list of ports, and the packet is transmitted over the selected port. In one example, the list is modified continuously as a background process based on network traffic. The list may be modified by determining a port which is under-utilized, determining a port which is over-utilized, and substituting in the list one or more instances of the port which is over-utilized with one or more instances of the port which is under-utilized. In this manner, a router can adaptively and evenly distribute the packet transmission traffic over the output ports.

Abstract: A router and method therefore for routing and switching a packet from an incoming link to an outgoing link. The router may include a plurality of network processing units, a plurality of switching engines, and a plurality of connections between the plurality of network processing units and the plurality of switching engines defining a rotational symmetric topology. The router may also include a means for connecting the plurality of network processing units to the plurality of switching engines, as well as means for connecting the plurality of switching engines to the plurality of line card units. In one example, the plurality of line card units is connected with the plurality of switching engines in a full mesh topology.

Abstract: A router including a lookup execution unit including a plurality of stages, a forwarding table memory arranged in hierarchy including addressable sectors, blocks, and entries, and a crossbar having an address crossbar for selectively coupling one of the plurality of stages to a sector of the memory so that data from the sector can be read. In one example, any one of the stages of the plurality of stages may be selectively and dynamically coupled with any one of the sectors of the forwarding table memory for providing an address to a particular sector of the memory to read data therefrom.

Abstract: A method for a router having a routing table and a forwarding table. In an embodiment, the method includes creating an entry for use in the forwarding table, the entry corresponding to multiple entries of the routing table. The entry may correspond to a set of entries of the routing table which specify overlapping IP addresses and a same next hop router, in one example. In another example, the entry may be an aggregate entry corresponding to a set of entries of the routing table which specify the same next hop router.

Abstract: A method for a router having a routing table and a forwarding table. In an embodiment, the method includes creating an entry for use in the forwarding table, the entry corresponding to multiple entries of the routing table. The entry may correspond to a set of entries of the routing table which specify overlapping IP addresses and a same next hop router, in one example. In another example, the entry may be an aggregate entry corresponding to a set of entries of the routing table which specify the same next hop router.

Abstract: A router including a lookup execution unit including a plurality of stages, a forwarding table memory arranged in hierarchy including addressable sectors, blocks, and entries, and a crossbar having an address crossbar for selectively coupling one of the plurality of stages to a sector of the memory so that data from the sector can be read. In one example, any one of the stages of the plurality of stages may be selectively and dynamically coupled with any one of the sectors of the forwarding table memory for providing an address to a particular sector of the memory to read data therefrom.

Abstract: A method for routing and switching data packets from one or more incoming links to one or more outgoing links of a router. The method comprises receiving a data packet from the incoming link, assigning at least one outgoing link to the data packet based on the destination address of the data packet, and after the assigning operation, storing the data packet in a switching memory based on the assigned outgoing link. The data packet extracted from the switching memory, and transmitted along the assigned outgoing link. The router may include a network processing unit having one or more systolic array pipelines for performing the assigning operation.

Abstract: A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of programmable functional units and register files arranged sequentially as stages, for processing packet contexts (which contain the packet's destination address) to perform operations, under programmatic control, to determine the destination port of the router for the packet. A single stage of the systolic array may contain a register file and one or more functional units such as adders, shifters, logical units, etc., for performing, in one example, very long instruction word (vliw) operations. The processor may also include a forwarding table memory, on-chip, for storing routing information, and a cross bar selectively connecting the stages of the systolic array with the forwarding table memory.

Abstract: A central processing unit of a computer includes a single-ported data cache and a dual-ported prefetch cache. The data cache accommodates a first pipeline and the prefetch cache, which is much smaller than the data cache, accommodates both the first pipeline and a second pipeline. If a data cache miss occurs, a row of data corresponding to the specified address is stored in the data cache and the prefetch cache. Thereafter, if a prefetch cache hit occurs, a row of data corresponding to a prefetch address is loaded into the prefetch cache. The prefetch address may, for instance, be generated by adding a fixed increment to the specified address. This operation frequently results in the prefetch cache storing data soon requested by a computer program. When this condition is achieved, the data corresponding to the subsequent address request is rapidly retrieved from cache memory without incurring memory latencies associated with the external cache, the primary memory, and the secondary memory.

Abstract: A method of ensuring instruction cache consistency in a processor includes executing a flush instruction whenever a program executed by the processor stores data to a given data address and, subsequently, executes another instruction requiring a data fetch from the same address. According to this method, a write cache prevents any addressed instruction from residing in the write cache and the instruction cache at the same time. Thus, when an instruction having a store address not already present in the write cache is retired to the write cache, the write cache instructs the instruction cache to invalidate any data stored therein having a same address. The flush instruction prevents execution of any other instructions after the store at least until the store to the memory address has been allocated to a write cache of the processor, thus enabling the write cache to invalidate the subsequent instruction at the same address in the instruction cache.

Abstract: Data is collected from multiple data packets for group transfer on a data path so as to maximize utilization of the data path. A particularly suitable data path is one that is coupled to transfer data to a graphics frame buffer. In collecting data from multiple data packets, data from individual packets are designated for loading onto the data path. In specific embodiments, data from a packet will be designated for loading onto the data path only if it is determined that the data is noncacheable data, the data would not overwrite other valid designated but not yet loaded data, or the resulting data to be transferred as a group would target data locations within a permissible locus of data locations, such as a contiguous range of addresses. The designated data are loaded onto the data path as a group for actual transfer. In a specific embodiment, there is a mask associated with each data packet that indicates which portions of each packet's possible data actually contain data to be transferred.

Abstract: A non-inclusive cache system includes an external cache and a plurality of on-chip caches each having a set of tags associated therewith, with at least one of the on-chip caches including data which is absent from the external cache. A pipelined snoop bus is ported to each of the set of tags of the plurality of on-chip caches and transmits a snoop address to the plurality of on-chip caches. A system interface unit is responsive to a received snoop request to scan the external cache and to apply the snoop address of the snoop request to the pipelined snoop bus. A plurality of response signal lines respectively extend from the plurality of on-chip caches to the system interface unit, each of the signal lines for transmitting a snoop response from a corresponding one of the on-board caches to the system interface unit. The set of tags can be implemented by dual-porting the cache tags, or by providing a duplicate and dedicated set of snoop tags.

Abstract: A non-inclusive cache system includes an external cache and a plurality of on-chip caches each having a set of tags associated therewith, with at least one of the on-chip caches including data which is absent from the external cache. A pipelined snoop bus is ported to each of the set of tags of the plurality of on-chip caches and transmits a snoop address to the plurality of on-chip caches. A system interface unit is responsive to a received snoop request to scan the external cache and to apply the snoop address of the snoop request to the pipelined snoop bus. A plurality of response signal lines respectively extend from the plurality of on-chip caches to the system interface unit, each of the signal lines for transmitting a snoop response from a corresponding one of the on-board caches to the system interface unit. The set of tags can be implemented by dual-porting the cache tags, or by providing a duplicate and dedicated set of snoop tags.

Abstract: A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing pipeline of the microprocessor in a fashion similar to the instruction which caused the miss (the "miss instruction"). The help instructions use the source operands of the miss instruction to form the miss address, thereby providing the fill address using the same elements which are used to calculate cache access addresses. In one embodiment, a fill help instruction and a bypass help instruction are generated. The fill help instruction provides the input address to the data cache during the clock cycle in which the fill data arrives. The appropriate row of the data cache is thereby selected for storing the fill data. The bypass help instruction is dispatched to arrive in a second pipeline stage different from the stage occupied by the fill help instruction.