Patents by Inventor William L. Nicoll

William L. Nicoll has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10497779
    Abstract: A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, William L. Nicoll, Hanfei Wang
  • Patent number: 10177154
    Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael V. Aquilino, Veeraraghavan S. Basker, Kangguo Cheng, Gregory Costrini, Ali Khakifirooz, Byeong Y. Kim, William L. Nicoll, Ravikumar Ramachandran, Reinaldo A. Vega, Hanfei Wang, Xinhui Wang
  • Patent number: 10153340
    Abstract: A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: December 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, William L. Nicoll, Hanfei Wang
  • Publication number: 20180337232
    Abstract: A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Michael A. GUILLORN, William L. NICOLL, Hanfei WANG
  • Patent number: 10121855
    Abstract: A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: November 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, William L. Nicoll, Hanfei Wang
  • Publication number: 20170365606
    Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.
    Type: Application
    Filed: August 30, 2017
    Publication date: December 21, 2017
    Inventors: Michael V. Aquilino, Veeraraghavan S. Basker, Kangguo Cheng, Gregory Costrini, Ali Khakifirooz, Byeong Y. Kim, William L. Nicoll, Ravikumar Ramachandran, Reinaldo A. Vega, Hanfei Wang, Xinhui Wang
  • Patent number: 9825041
    Abstract: Various embodiments include methods and integrated circuit (IC) structures. In some cases, an IC can include: a substrate; a deep trench within the substrate; a buried oxide (BOX) layer adjacent the deep trench; a first fin structure over the deep trench; a second fin structure over the BOX layer; an ONO layer over the first fin structure; and a gate electrode contacting the ONO layer.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: November 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: William L. Nicoll, Byeong Y. Kim
  • Patent number: 9818741
    Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: November 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael V. Aquilino, Veeraraghavan S. Basker, Kangguo Cheng, Gregory Costrini, Ali Khakifirooz, Byeong Y. Kim, William L. Nicoll, Ravikumar Ramachandran, Reinaldo A. Vega, Hanfei Wang, Xinhui Wang
  • Publication number: 20170194429
    Abstract: A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.
    Type: Application
    Filed: June 9, 2016
    Publication date: July 6, 2017
    Inventors: Michael A. Guillorn, William L. Nicoll, Hanfei Wang
  • Publication number: 20170194431
    Abstract: A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.
    Type: Application
    Filed: January 3, 2017
    Publication date: July 6, 2017
    Inventors: MICHAEL A. GUILLORN, WILLIAM L. NICOLL, HANFEI WANG
  • Patent number: 9607993
    Abstract: Capacitor strap connections for a memory cell and device structures for making such capacitor strap connections. A deep trench capacitor is formed in a substrate. A collar comprised of an electrical insulator is formed at least partially inside an upper section of a deep trench in which the deep trench capacitor is formed. A portion of the collar is removed to define a notch extending through the collar, and a connection strap is formed in the notch. A fin is formed from a portion of the substrate, and is coupled by the connection strap with an electrode of the deep trench capacitor that is located inside the deep trench.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: March 28, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Byeong Y. Kim, William L. Nicoll
  • Patent number: 9570550
    Abstract: A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, William L. Nicoll, Hanfei Wang
  • Publication number: 20170005098
    Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 5, 2017
    Inventors: Michael V. Aquilino, Veeraraghavan S. Basker, Kangguo Cheng, Gregory Costrini, Ali Khakifirooz, Byeong Y. Kim, William L. Nicoll, Ravikumar Ramachandran, Reinaldo A. Vega, Hanfei Wang, Xinhui Wang